More mess in the FET modeling lab

In FET modeling lab looking complicated,  I showed how messy the current-versus-gate-voltage plots were:

The middle of the curve fits well to the exponential sub-threshold conduction models for an nFET. But what is going on at the ends?

Since we don’t use FETs in subthreshold conduction (at least not in this course), the lab above was really only useful for showing how sensitive FETs are to temperature.

Today I decided to try characterizing the same nFET connected as a diode (connecting the gate to the drain to make a 2-terminal device which is always in saturation above the threshold voltage).  Since I don’t have at home one of the really nice Agilent E3631A bench power supplies that the lab has (and at $1500 I’m not about to get one), I started out using an op amp as a voltage source for the diode-connected nFET.  But the op amp was only capable of delivering 30mA, and I wanted to test higher than that, so I made my own adjustable regulated supply:

Circuit for testing the diode-connected nFET. The “positive” feedback connection is correct, because the output pFET serves as an extra inversion.  The feedback capacitor is just there to suppress oscillation—I don’t know that it is needed, but I felt better putting it in.
Current is measured as the difference in voltage across the load resistor, and different load resistors were used to get different ranges.

This home-brew power supply worked well enough for me to observe some really strange behavior:

The straight line for low currents is the expected subthreshold conduction.
The spreading of the curves at high current are due to the same threshold shifting that we saw before.
But what is going on between 12mA and 50mA? (click on picture to enlarge)

I’m really mystified by the reduction in V_gs (and V_ds) with increasing current between 12mA and 50mA. It doesn’t seem to be a thermal effect, as it is seems stable over time for low enough currents (under 30mA), and the effect is still visible (though shifted over by the change in threshold voltage) for the warm FETs when the current is lowered again after a higher current.

I was not aware that a simple diode-connected FET could exhibit type-S negative resistance!  I’ve not seen that characteristic of nFETs described anywhere, and a quick Google search did not find me any references.  It seems to occur over a constant range of currents, independent of the threshold shift from thermal effects. I wonder if it is useful for anything.  It might be fun to try to make a negative resistance oscillator with it, though with the huge current needed, it would not be a particularly low-power oscillator.

Unfortunately, this interesting effect is not the simple story I was hoping for in a first circuits course for non-EEs.

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