In Rethinking the power-amp lab again, I described the failure of my class-D power amp on Thursday afternoon, and the dilemma I faced in whether to revise the lab or cut it from the course. Some of the students favored cutting it (they’re hitting end-of-quarter crunch time), but I know that they would not learn any of the material that lab is intended to help them understand without actually doing the lab. Also, if I had one less lab report to evaluate them on, I’d probably have to add a final exam, which I don’t think they would like any better.
So Thursday night I woke up around 3 a.m. and thought about ways to salvage the power-amp lab. First, I had to figure out what differences there were between the circuit I had working at home, and the same board, with slightly different power-supply options in the lab on campus. The only real difference was the voltages for the power-amp stage (the comparator and power FETs). At home, I was using a 6.6V power supply—the same one I was using for the pre-amp stage, so that the FET sources were at 0V and 6.6V (and the loudspeaker had a DC bias that is undesirable). On campus, the preamp had a +6V supply, and the comparator and FET sources were at ±4V, but I wanted to be able to go to ±7V or even ±9v.
I came up with some ideas for potential solutions.
- The first was a fairly trivial one: just have them use a single 6V power-supply the way I had, and not worry about the DC offset to the loudspeaker. I don’t like this solution very much, because it doesn’t provide much power to the speaker (about 0.5W), and has that DC bias.
- A minor variant of the first idea is to add a large series capacitor to the loudspeaker. Our big electrolytics are 470µF, and we’d have high-pass filtering with a corner frequency of about 66Hz, which is ok for the small speakers (whose resonant frequency is around 155Hz. The 16V limit for the electrolytic capacitor is no problem, since the pre-amp using an MCP6004 chip shouldn’t really be run with more than 6V.
- Another minor variant eliminates the series capacitor by using a ±3V supply, with the preamp powered from -3V and +3v. This has the advantage of eliminating the need for a virtual ground in the pre-amp, as well as powering the loudspeaker cleanly. But we are still limited to 0.5W.
- The second major solution was to change the output stage from having a simple cMOS inverter (with the pFET and nFET gates connected together) to using a separate comparator to drive each of the FET gates. By changing the pull-up resistors on the open-collector outputs of the comparators, I could adjust the rise and fall rates. By using a very small pull-up, the voltage would rise rapidly, fall slowly, and not get very low. By using a larger pull-up, the voltage would fall rapidly, rise slowly, and get quite low. Since I don’t want the nFET and pFET on at the same time, I want to turn the FETs off quickly, but on slower, so that one is off before the other turns one. That lead me to a design with a large pull-up resistor for the nFET gate and a small one for the pFET gate. (“Large” and “small” are relative terms here—mine were within a factor of 10 of each other, since they are constrained by how much current the comparator can sink and by how fast we want the gate voltages to change.
On Friday morning, I went into the lab and tried out potential solutions 1, 3, and 4. (Since we have a dual supply handy there is no reason not to use it.)
Since solution 1 is essentially identical to what I had debugged at home (but with a 6V supply instead of a 6.6V supply) it worked fine. Splitting the supply into a +3V and a -3V supply with the loudspeaker connected to the middle eliminated the DC bias on the speaker without changing anything else, so it worked fine also.
It took me a while to debug the design with the separated comparators, mainly because I had forgotten to allow for one very important constraint: the inputs to the comparators have to be between the power rails of the comparator. With the preamp powered from 0V and 6V, and the comparators powered at ±3V, that constraint was violated. I upped the voltage for the power stage to ±6V and the comparators worked ok. I did have to fuss around a bit with pull-up resistor for the nFET, since we need to make sure that the comparator will have an output low voltage < 1V above the bottom power rail. That means that the size of the pull-up for the nFET needs to be based on the power-supply voltage and the current sunk by the comparator (which we should assume is around 5–6mA if the output voltage is below 1 v, up to 7.5mA if we can tolerate a larger output voltage from the comparator). The pull-up for the pFET can be much smaller (so that the pFET turns off quickly), but that means that the pFET gate does not go close to the lower power rail. Still, the pFET works fine as long as the gate is at least 3V below the upper power rail, so if we can get away with a fairly small resistor. I probably should play around with the resistors some more on Monday, so that I can give the students better guidance on how to design them based on experience, and not just theory.
The separate-comparators option is the closest to a real power-amp design, and is the one I think I’ll write up a lab-handout addendum for this weekend. I’ll try to get that done and an EKG lab handout, and make a final decision about whether to drop the power-amp lab (adding a final instead) or keep it.
I’ve definitely rejected the idea of a bipolar current gain before the FET gates (too complex for a 1-week lab) and pretty much rejected the idea of class-A amplifier (both the DC offset and the heating of the FET are problematic). I will think about switching to teaching a bipolar class-AB power amp next year, though, instead of a class-D.