Today was a rather disappointing day for me. I spent most of the day working on developing a decent power-amp lab, and I’m not happy with what I’ve got so far. You may remember from my earlier post (Op-amp lab), that I was planning to have the students start with an AC-coupled op amp using an electret mic. Something like this:
Today I wanted to try two things: getting rid of the extra op amp that creates the Vbias supply, and adding two FETs to make a higher-power output stage . My attempts to do the design in Circuit Lab were stymied by the CircuitLab simulator’s inability to solve for the DC values, insisting on producing gigavolt and teravolt solutions (when it didn’t just fail with nonfinite solutions).
So I built a circuit and tested it. I did the debugging using my BitScope Pocket Analyzer (which I blogged about already). My initial design did not seem to be turning on the pFETs strongly enough, so I adjusted one of the bias resistors to lower the voltage needed. That didn’t really help. The problem seems to be that the power supplies I was using (I tried a battery pack and the USB 5v supply through the BitScope) are not beefy enough, and the voltage dropped from 5v to 3.5V whenever there was a large output, like when a loud feedback squeal was produced. I switched to using a wall wart that claims to be able to produce 5V and 2.5A, and got the amplifier working, though the wall wart provides an annoying hum (it is not a regulated supply).
I then tried a 6.6v switching supply that I had, and it was beefy enough—beefy enough to start releasing smoke from the FETs, as I had not resized the bias resistors for the 6.6v supply. I cut the power and let things cool down, and tested again with the 5v supply. I had not killed the FETs (so my decision to get fairly heavy duty power transistors was probably a good one). Here is the design I was playing with:
I’m also seeing a lot of coupling through the power supply lines, with the switching transients from the output FETs turning on and off visible at the microphone, though the output voltages show no glitches there.
Changing one resistor in the final bias network (to keep the pFET and nFET from both turning on strongly at the same time) lets the amplifier work fine with the 6.6v regulated supply. That supply also keeps the coupling of the FET switching noise out of the power lines: the power lines only show 1–2mV of ripple even when I have a feedback squeal that is 6v peak to peak. The FETs don’t even get perceptibly warm.
I’m still not sure that the amplifier is working correctly, though, as the spectrum analysis of the input and output of the amplifier (one of BitScope’s features) indicates a much purer signal on output than on input. I’m worried that my frequency response is nowhere near flat, so I’m going to have to put in a signal other than the microphone input, look at the output, and see if it is reasonable.
I hooked up my function generator with a big divide-down voltage divider in place of the mic and resistors (before the DC-blocking capacitor). It took me some playing around with the central resistor value of the FET bias network to both eliminate crossover distortion and keep the FETs from getting hot. The values I had calculated based on the FET thresholds resulted in crossover distortion—I had not allowed enough of an overlap with both FETs slightly on. I fixed the problem by adjusting the central resistor—I think that this lab may be a good one for using a trimpot, as swapping out resistors on the breadboard was a pain. Students will have to be warned to start with the central resistor too big (to ensure that both transistors are off in the middle of the voltage range) and gradually decrease the resistance until the crossover distortion goes away (but not so much that the transistors start getting hot). They’ll want to size the other resistors so that a 10kΩ trim pot has a reasonable range.
I also tried using the Bitscope to generate signals, rather than my separate function generator. It produces somewhat cleaner signals than the Elenco FG-500, but there is a nasty click between frames, when the BitScope is dumping data to the host computer and not sending out the waveform.
Although I have a working circuit for the power amp, it took me longer to get there than I’d like, which means that the full design project is probably too much for a 3-hour lab. If the lab is just the output stage design, added to a working op amp design from the previous lab, it may just be doable. We may have to do the computation of the resistors for the bias network a little more carefully than I did, which would mean carefully characterizing the I-vs-V curves for the FETs. Perhaps there needs to be a design worksheet for the students to work through all the ramifications of class AB output stages.
The other depressing thing today (other than the rainy weather), was that I dropped one of the electrode holders off my desk. As Gabriel Elkaim had predicted, it snapped at the neck:
I still have enough for the course, but I suspect we’ll lose a couple more during the labs this year. I’ll have to redesign to round the corners wherever I currently have a sharp corner (to eliminate stress raisers), and make the neck a bit wider as well.