I think I rescued the electret microphone lab by having the students automate the I-vs-V measurements with the Arduino and the following circuit (see Mic modeling lab rethought):
I considered having the students measure the FETs for the power-amp lab using a similar technique, but with the potentiometer adjusting the gate voltage, rather than the drain voltage. I spent most of yesterday playing with variants of that idea, and I’m not sure it’s going to work.
Here is a sample of some of the data I collected:
There are several problems with this way of characterizing the FETs:
- The drain-to-source voltage VDS is not being held fixed. Since the current is a function of both the gate-to-source voltage VGS and VDS, having both varying makes modeling difficult.
- The resistors the students have to use are ¼-watt resistors, so we can only put large currents through them if the resistors are very small (say 1Ω for 0.5A, 0.25Ω for 1A). The resistance of the wiring starts to matter with resistances that small.
- The Arduino measurements are somewhat inaccurate when we get down to variations in just the least-significant bit. Many of the curves above deviate from the consensus when the Arduino is measuring small voltages.
- I wasn’t measuring VGS directly but computing it from VG-VS, which limits the range of VGS, since VS increases rapidly when the transistor is turned on. With the voltage limitations of the Arduino ADC, I was limited to VGS being just a little more than the threshold voltage of the nFET.
For most of the range that I measured, I got a very nice fit to the standard subthreshold conduction model, with drain-to-source current IDS being exponentially related to VDS. This model fits pretty well for 30nA ≤ IDS ≤ 10mA, almost 6 decades! I have no idea what is happening below 30nA, but there are probably leakage currents in the package or breadboard that can account for the excessive current there. No one uses power FETs for switching currents that small, so it hardly matters.
Of course, the FET is really designed for larger currents than 10mA—one doesn’t need a power FET for currents that small. What I was hoping to see was the standard curve where current is proportional to the square of the gate voltage above threshold: . But look at the mess we have at the high end of the curve!
I spent a long time trying to figure out where in the circuit the hysteresis was coming from. I pretty quickly ruled out all kinds of charge-storage mechanisms, because every place where charge might be stored was directly connected to conductors (or semiconductors that were biased to conduct). I’m not running high enough voltages to inject charges into the insulating layers.
At first, I suspected that I was overheating the little ¼-watt resistors. I was, but that wasn’t the problem. I had one 2-watt 23Ω resistor (labeled as 22Ω, but I trust my Fluke multimeter more than I trust color-code bands), and that did not get noticeably warm, but exhibited the same behavior as the ¼-watt 22Ω resistor.
Then I realized that the nFET had strongly temperature dependent behavior. It is even evident on their datasheet:
The datasheet has the threshold current dropping at 5.2mV/ °C, so when we are just a little above threshold, as in our measurements, warming the transistor with a fixed gate voltage causes the current through the transistor to increase substantially. Note that the increase in on-resistance with temperature matters more at higher gate voltages, but that would involve currents of about 16A, which is much more than we want to work with in this lab.
With the 1Ω load I allowed the current to go as high as 1.06A (though not for long, as I did not want to burn out the resistor dissipating 1 watt in the ¼-watt resistor. Subtracting the drop across the load resistor from the 6.6v power supply results in VDS=5.54V, and the FET is dissipating 5.87 watts. The datasheet says that the FET should be able to handle 5A at that voltage, but they’re assuming that the FET has been surface-mounted to a square-inch of 2-oz copper on a PC board, to get a junction-to-ambient thermal resistance of 45°C/W. I tried measuring the case temperature with an infrared thermometer, but the FET is too small to aim the sensor well (the parallax for the aiming laser was extreme)—it was at least 80°C after a few seconds at 0.6A. The shift in the threshold voltage was about 0.6V, which would be consistent with a rise in the junction temperature of about 115°C to 135°C (close to the 150°C maximum for the device).
I don’t want to be giving the bioengineers thermal resistance calculations to do, and I don’t want them to be dealing with huge shifts in transistor parameters as the transistors heat up. So I’m going to need to think about this lab a lot, to turn it into something reasonable for the students to do. Either that, or I have to give up on the FET lab and the power-amp lab, and find two other reasonable labs to use in their place.