I’ve been puzzling over the source of the negative dynamic resistance in the PSMN022-30PL nFETs that I reported on in Testing nFET with function generator, which looks a lot like what I saw with the NTD5867NL nFETs in More mess in the FET modeling lab, but did not see with the AOI518 nFETs in Diode-connected nFET characteristics.
I replottted the I-vs-V curves for the diode-connected PSMN022-30PL as an R-vs-V curve, to get a better feel for the magnitude of the resistances.
Looking at the PSMN022-30PL data sheet in more detail, I can see that the nFET was not intended to be used at Vds=1.8V. When the nFET is on, with the 20mΩ to 30mΩ on-resistance, the maximum current of 30A would limit Vds to about 0.9V, and the power limitation of 41W would limit Vds to about 1.1V. We’re nowhere near the current or power limits, of course, but power nFETs are not usually kept in the range where they are just beginning to turn on.
I looked at the parasitic devices that come with a power nFET:
I did not get much help from friends on the EE faculty, who suggested that the parasitic BJT was latching up. But latchup is basically irreversible and occurs at large voltages—I’m barely turning the nFET on and I can trace the negative resistance region back and forth with no problem.
I have a conjecture now, but I don’t have enough information to really confirm it. I think that the parasitic JFET is controlling the current in this region. The JFET is in series with the MOSFET, and its resistance increases as Vds increases. Normally Vds is kept small enough that the JFET resistance is not a problem, but I’m looking at a region where Vds is somewhat larger than normally used, so the JFET may be controlling the total resistance—the depletion regions around the p– body (that form the body diode) may be large enough to almost pinch off the drain connection to the channel. As current flow through the JFET increases, Vds drops until the depletion regions separate making a clear path between the channel and the drain, and the JFET is no longer the main resistance—the other parasitic resistances dominate and Vds goes up with current again.
This explanation helps me understand why some power FETs exhibit the negative dynamic resistance and some don’t—the parasitic JFETs are very dependent on the geometry of the channel-to-drain connection. Indeed, trench nFET designs decrease the effect of the parasitic JFET considerably.
I’m still a bit confused, though, as I have to get the voltage up to about 1.8V (and current to about 6mA) before the negative-resistance behavior starts. Where is the state information stored that determines whether the resistance is 50Ω or 27kΩ when Vds is 1.5V? Could it be accumulated charges along the oxide that determine whether the channel (of the MOSFET) is on or not?