I have spent some time this week thinking about a lab for characterizing nFETs (and pFETs) for the applied electronics course, because I was not very happy with the preliminary work in Possible new FET lab for electronics course and pFET Ron_vs_Vgs. There were a couple of things that bothered me:

- Should we be looking at equivalent resistance or current? which is more consistent across different test conditions? which is more useful for continued design?
- Does it matter what circuit we use for making the measurement? What are the advantages or disadvantages of choosing different power supply values, different load resistors, or different transistor configurations?

The most basic choice is between a common-source or common-drain amplifier setup, both of which are special cases of the same circuit:

The testing I did before was with a common-source circuit. The output voltage range is from very close to 0V up to Vdd, which means that either V_{dd} has to be limited to the range of the analog-to-digital converter or a voltage divider is needed to divide down V_{d}. The current we are interested in is . Taking the difference of two measurements increases the noise of the measurement, and if V_{dd} is large enough that voltage dividers are needed, then the current through the voltage divider also goes through the load resistor, making measuring low drain currents (when V_{gs} is small) difficult.

The common-drain circuit only requires measuring V_{g} and V_{s}, both of which can be within the analog-to-digital converter range even when V_{dd} is large, assuming that the load resistor (R_{s} in this case) is chosen sufficiently small. Determining V_{gs} requires a subtraction, but I_{d} does not. Avoiding voltage dividers (with their current stealing and the extra trouble of measuring the divider ratio) seemed like a good idea.

I tried making measurements with the common-drain configuration today, and found it surprisingly difficult. I kept getting huge amounts of noise on the V_{s} plot, whenever the FET was on. It appeared to be 120Hz interference, but I have no idea where the interference was coming from—the power supply did not show significant 120Hz ripple and large bypass capacitors on the power supply lines did not help. I finally managed to get rid of the problem by putting a 10µF capacitor between the source and drain, providing a negative feedback path that eliminated the problem. (The capacitor appeared to make no difference to the plots for common-source configurations.)

The common-source circuits, however, provided much cleaner plots than the common-drain circuits. The common-source circuits also allowed me to measure much higher drain currents, because I could go to a higher V_{gs} value without exceed the ADC range when V_{s} was constrained to be 0V.

For the range that I could measure, I got essentially the same current whether I measured drain current or source current, and pretty much independent of the voltage and load resistance I used. To first approximation, it looks like I_{d} is a function of V_{gs} in a way that the equivalent resistance that plotted in Possible new FET lab for electronics course is not.

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