I’ve been bothered for the past week (or more) about why my FET measurements in Possible new FET lab for electronics course, , More thoughts on measuring FETs, and Measuring a high-voltage nFET were not coming out the way I expected. In particular, I was measuring much higher on-resistances than I expected from the data sheet, and I was getting different results when I made small changes in my measurement setup, like changing the current-sense resistor.
My measurements were all for Id vs. Vgs (or R=Vds/Id vs. Vgs). Today, I decided to try measuring Id vs. Vds for different Vgs values, to see whether an Ron made sense (straight lines for Id vs Vds, at least for small values of Vds). Because I wanted to test with a wide range of currents, from very small to reasonably large, I could not use the function generator to sweep the desired voltage range—it can’t supply much current. Instead, I built the following test fixture:
Before using the test fixture, I calibrated the voltage dividers plus unity-gain buffers as producing an output that was d*V_in+b. Of the 4 amplifiers in the MCP6004 chip, I picked the three that gave the smallest offsets (b), wiring the inputs of the other amplifier to 3.3V and GND. The amplifier was powered off the 3.3V output of the Teensy LC board.
Here are the I-vs-V plots that I got:
The weird thing is that no matter what gate voltage we are looking at, there is a minimum Vds voltage, around 17mV. No current flows until that voltage is exceeded, and then the voltage stays almost constant until the resistance of the channel limits the current. If we try measuring the on-resistance with a tiny current, Itest, we get 0.017V/Itest as the on-resistance—the smaller the test current, the larger the on-resistance, and the resistance seems to be nearly independent of gate voltage (the phenomenon that confused me so much in my Id-vs-Vgs plots).
Enough current to measure the resistance depends on how strongly on the transistor is. If it is barely on (Vgs=2.43V), then 200mA is enough, and the on-resistance can measured as around 160mΩ–215mΩ. At logic-levels (Vgs=3.35V), then we need around 450mA, and the on-resistance is around 49mΩ. When fully on (Vgs=9.15V), then 900mA may not be enough—the best estimate I can get there is around 25mΩ.
I redid the measurement with a 1.8Ω 50W resistor for the fully-on transistor. This produced a curve much like the one for Vgs=3.35V, but with the current going up to 4.76A (with a power dissipation of about 1W in the nFET). I estimated about 36mΩ on-resistance at Vgs=8.94V. Of course, I’m not very confident of the 1.8Ω value, as wiring and breadboard resistance adds a substantial error at those low resistances, so the on-resistance may be even higher. The datasheet reports on-resistance of about 6mΩ for Vgs=9V, measured at 20A, which is not a measurement I’m equipped to do.
The cause of the 17mV minimum for Vds is not clear—it has not appeared in any of the simplified models of FETs that I’ve seen. My current best conjecture is that there is a Schottky diode formed by the bonding wires contacting the silicon transistor. There is usually heavy doping of the silicon to avoid Schottky diodes at the bonding wires, but perhaps 0.02V was the best that they could do. Does anyone reading this know enough about power nFETs to either confirm my conjecture or offer a better one?
Incidentally, the requirement that the measuring current be large (around 0.5–1A) means that the simple FET measuring lab I was thinking of putting in the course won’t work. For one thing, the students don’t have any power resistors for handling the current sensing. The only device they have capable of dissipating much power is their loudspeaker, and it is not a well-defined enough impedance to use for measuring current in the FETs. I’m glad I haven’t written up that lab for the book yet!
[Update 2016 August 2: I didn’t really believe this set of results, so I did a negative control that I should have done earlier, replacing the nFET with a drain-source short. It also shows the 0.02V minimum, indicating that this is a limitation of my test jig, not a property of the nFET! I’ll have to come up with a better test jig.]