In Why my nFET measurements were bad I observed a fixed minimum drain-to-source voltage for my nFET measurements, and claimed that this was the reason I couldn’t get consistent results for the on-resistance of nFETs when measuring with small currents.

I worried about the result, though, because I really saw no reason for there to be a 20mV minimum Vds voltage. So I did what I should have done right away—set up a negative control. I used a piece of wire to connect the source and drain of the transistor being measured, and did the same Id vs Vds measurements. This should produce a simple resistance that is very small (a few mΩ for the resistance of the breadboard). But I got the same 20mV minimum voltage as with the nFETs!

The problem turned out to be in my compensation for the offset of the unity-gain buffers—it corrected the value well, but could not correct the range—the smallest ADC output is 0, so if the offset correction makes a 0 ADC value correspond to a positive voltage, then that voltage is the lowest that can be reported.

Today I decided to correct the range as well, by making sure that the op-amp inputs stayed away from 0. I added 470kΩ pullup to 3.3V to the voltage divider, so that with the input at 0v the output would be at about 83mV. The Thévenin equivalent of the 470kΩ and 15kΩ resistors is a 14.54kΩ resistor to 102mV.

I recalibrated the test fixture to get the dividers’ ratios and offsets and measured the nFET again. I tried to let the transistor and load resistor warm up for a while before starting recording for each gate voltage, to avoid thermal drift (there still seems to be some drift for the Vgs=2.89V trace).

I fit the equivalent resistance model by fitting , allowing for some residual offset in the Vds measurement. For computing the drain current, I not only used the corrected voltages for Vds and Vdd, but also subtracted off Vds/76.5kΩ, the approximate impedance of the voltage divider for Vds. The 80µA drain current for Vgs=0V is more than expected leakage for this nFET (1µA @20°C), and probably reflects the remaining imperfections of the test setup.

The maximum power that can be delivered to the nFET is a parabola determined by the 9V power supply and 10Ω load resistor—it passes through 0A at 0V and the power-supply voltage, with a maximum at half the power-supply voltage. I did have one run that traced out most of the parabola, including the peak at 4.5V, but I did not use that curve in this post, because it was collected before I added the noise-reducing capacitors at the inputs to the ADC.

The curve for Vgs=2.40V (weakly on) is the only one that shows much hysteresis due to thermal effects. The changes in resistance and threshold voltage due to temperature are most important when you are very close to turning off the transistor, and the heating is most when the equivalent resistance of the channel matches the load resistor.

The resistances I’m measuring (105mΩ at best) are still much higher than I would expect based on the data sheet, which specs 9.3mΩ max with Vgs=4.5V (measured at 30A).

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