# Gas station without pumps

## 2015 July 25

### Noise from PteroDAQ KL25Z

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 15:31
Tags: , , , , , ,

In a series of posts (most recently More on measuring PteroDAQ KL25Z input impedance), I’ve been measuring the input impedance of my various ways of measuring AC voltage, and having some trouble getting a reasonable value for using the PteroDAQ as a measuring device.  In the most recent post, I noted that hardware averaging seemed to make the measurements worse, not better, when the input impedance was high.

I decided to map out how bad this measurement error was, by changing the source resistance and seeing how the voltage measurement changed. I picked a low frequency (55Hz) with a high sampling rate (6001.5Hz), so that aliasing was not an issue.

The voltage measurements are fine up to a source impedance of 10kΩ without averaging, but only to 1kΩ with 32× hardware averaging.

My conjecture about the problem with the 32× averaging was that the KL25Z sample-and-hold circuitry was injecting interference onto the pin, and that too high a source impedance did not provide sufficient current to eliminate this noise before the next sampling of the pin.

I tried fixing the problem by adding a small capacitor between the pin being measured (PTE0) and ground. The idea is that the capacitor can short out the high-frequency interference, using charge from the capacitor to cancel the noise rather than from the source. If the capacitor is too large, then the low-pass RC filter of the source impedance and the capacitance will reduce the signal, but if it is too small, then the sample-and-hold will be confused by the noise from the previous sample. With the 55Hz signal and a 100kΩ source impedance, I tried a number of capacitors, looking for the one that would maximize the voltage reading with 32× hardware averaging. I settled on 470pF, which would give a corner frequency of 3.39kHz (approximately my Nyquist frequency).

Putting in a 470pF capacitor to bypass the noise from the sampling helps when there is no averaging, but not so much when there is averaging.

With the 470pF capacitor, the source resistance can get as high as 100kΩ before the noise injection becomes a problem, when not using hardware averaging (at the 6kHz sampling rate—higher sampling rates would start seeing problems at lower impedances. In general, I think that sampling period should be at least 3.5 times the RC time constant of the source resistance and the added capacitance. For single-ended, 16-bit measurements with short sample times, the KL25Z hardware averaging has a period of 25 ADC clock cycles and PteroDAQ is set up to use a 6MHz ADC clock, so the samples are at 240kHz, which would suggest a maximum source impedance of 2.5kΩ for a 470pF capacitor using hardware averaging. This seems consistent with the measured data.

I realized this morning that I did not need to just conjecture the noise on the pin—I could stick an oscilloscope on it and measure it. I used a 47kΩ series resistor (so that the 1MΩ || 10pF load of the Bitscope oscilloscope would not make a huge difference) and a 10 Hz input from the FG085.  I set the PteroDAQ sampling rate to 3750Hz, so that there would be about equal time for the 32 samples and for recovery between them.  I captured single traces and got fairly consistent results.  Here is an example:

This trace at 50mV/division and 20µs/division shows the 240kHz noise from the sample-and-hold circuitry for the first half, and the much smaller noise when not sampling for the second half. This trace was done without the 470pF capacitor.

The noise injected by the sample-and-hold circuitry is about 190mV peak-to-peak with the 47kΩ resistance, or about 4µA.

Adding the 470pF capacitor reduces the peak-to-peak noise to about 16mV or 340nA, but there is enough of a bias to the noise that the error is much larger, as seen by the slow decay back to the correct value in the following trace:

At 10mV/division and 20µs/division, this trace shows both the reduction in noise from using a 470pF capacitor and slow recovery to the correct voltage at the end of the 32 samples. The time constant for 470pF times 47kΩ is about 22µs, about 5.3 times the sampling rate (or about 20 times longer than desirable for accurate reading).

The injection of noise back into the circuit being tested is a particularly nasty property for test equipment to have. One could avoid it by adding a unity-gain buffer before the pin, which would have three good effects:

• The input impedance would now be the impedance of the op amp, which can be in the 10GΩ range (for the cheap MCP6004 op amps we use in class)
• If there was noise from the microprocessor, it would not be injected into the circuit being tested.
• The source impedance for the analog-to-digital converter would now be around 40Ω (for the MCP6004 op amps), so all these noise problems would go away.

There is one downside to using a unity-gain buffer: you get some non-linearity near the power rails, so the range of useful operation is reduced somewhat.

So when using the PteroDAQ, it is important to pay attention to the source impedance.  When the source impedance, R, is high, one can either

• add capacitance to reduce the switching noise of the sample-and-hold circuitry (resulting in an RC time constant >3.5 times the sampling period, which can be user-specified (no averaging), 4.1667µs (single-ended channels), or 5.6667µs (differential channels) on the KL25Z; or
• add a unity-gain buffer to separate the input from the pin.

The noise consideration is a bigger constraint on operation than the input impedance of the analog-to-digital converter pins, which made my attempts to characterize the input impedance somewhat quixotic.

## 2015 July 23

### More on measuring PteroDAQ KL25Z input impedance

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 17:04
Tags:

In a series of posts (most recently Measuring PteroDAQ KL25Z input impedance), I’ve been measuring the input impedance of my various ways of measuring AC voltage:

meter Z
DT-830B 0.42MΩ || 31.59pF
DT-9205A 13MΩ || 22pF
BitScope BS-10 oscilloscope 1.025MΩ || 9.8pF
PteroDAQ KL25Z single-ended
measured with 100kΩ
2.6MΩ || 8pF

Last night and today, I’ve been struggling with trying to measure the input impedance of the differential inputs (spoiler: the problems had nothing to do with inputs being differential). I set the KL25Z board up so the PTE20 was the signal from the function generator, and PTE21 was the output of a voltage divider from the 3.3V power (about 1.9938v). Because the estimated input impedance for a single-ended channel was 2.6MΩ || 8pF, I started by measuring the voltages for adding 0Ω and for adding 3.3MΩ in series using the same aliasing tricks to measure high frequencies as in the previous post:

Here was my first WTF moment: why did the voltage readings drop essentially to 0 around 44kHZ, and then go back up?

The behavior of the voltages with no series resistance mystified me for quite a while. Where was I getting that nearly perfect zero around 44kHz? How did the cheap differential amplifier in the chip produce such a near-perfect zero?  I was convinced it was from the differential amplifier, because I saw no zero at 44kHz for a single-ended input.

It took me a long time to realize that I had been measuring with the 4× averaging turned on (the default), rather than the 1× averaging that I had intended.  The 4 samples being averaged are essentially a low-pass, finite-impulse response filter with the transfer function $(1+z^{-1}+z^{-2}+z^{-3})/4$, with a sampling rate that is the time between the samples set by the hardware averaging. That transfer function has zeros corresponding to ¼, ½, and ¾ the sampling rate. For 16-bit differential measurements, there are 34 cycles for each sample, which at 6MHz gives a hardware sampling rate of 176470.59Hz, and ¼ the sampling rate is 44117.65Hz, right where I was seeing a zero.

So the first mystery was solved: what I was plotting for the no-resistance case was the response of the averaging filter:

The FIR response of the averaging filter is a very good fit to the observed data for the no-series resistance voltages.

I decided to use the data before the cutoff of the averaging filter to get an estimate of the input impedance:

At 155kΩ || 760pF, this input looked like a lot lower impedance than the estimates I’d made for a single-ended input—so much so that I had trouble believing in such a low input impedance.

Since the 4× averaging limited the high-frequency response, I redid the measurements with 1× averaging:

With no hardware averaging, the voltage data looks usable out to 100kHz.

I did the impedance estimation as before by fitting to the voltage ratio seen with the 3.3MΩ resistor and with no series resistor:

With no averaging I get a very different input impedance than with 4× averaging!

I was very surprised to get a different estimate for the input impedance with no hardware averaging: from 155kΩ || 760pF with 4× averaging to 900kΩ || 440pF without averaging. I was particularly mystified by the change in the low-frequency resistance, as measurements of 5Hz signals should not be seeing changes from differences in averaging.

Since I had already been fooled once by thinking something was due to the differential amplifier, when it was actually something else, I decided to check what the single-ended input (just PTE20, rather than PTE20-PTE21) was doing at a single frequency (55Hz) with the 3.3MΩ series resistor:

I tried a number of different sampling frequencies, to see if there was a problem with my understanding of the effects of aliasing. Aliasing made sense to me, but the decreasing amplitude with more averaging did not.

I got pretty much what I expected in terms of the effects of sampling frequency. Being just a little off from the input frequency gave me about the same results as if I heavily over-sampled the waveform, but I got considerably attenuated results from using a sampling frequency near a small multiple of the input frequency as the samples had wildly different values from the preceding sample, and the sample-and-hold circuit didn’t have a long enough sampling time (667ns) to converge.

The weird behavior that confused me was the reduction in RMS voltage as hardware averaging increased. I only saw this behavior with the 3.3MΩ series resistor, not with direct connection of the function generator to the pin.

The datasheet for the KL25 processors does warn against using high-impedance sources for the ADC inputs, especially with short sampling times, because the sampling capacitor needs time to charge. They also suggest adding a 10nF capacitor to the inputs when the source impedance is high—then the sampling capacitor shares charge with that input capacitor, rather than having to be charged through the high-impedance source. With a 3.3MΩ source, a 10nF capacitor would provide a corner frequency of 4.8Hz—lower than most of the signals I’m interested in measuring.

But the limitations on the charging of the sampling capacitor are worth thinking about. The pin capacitance that is present just as parasitic capacitance is on the order of 6–20pF, for an RC time constant around 20µs–70µs with the 3.3MΩ source. But the interval between hardware averaging samples is 25 (6MHz) cycles, only 4.167µs. So if the sampling adds noise to the input pin (perhaps capacitive coupling from the gate of the sampling switch), then the 3.3MΩ source doesn’t provide enough current for the pin to recover from the kick, and doing more averaging just makes things worse. With long intervals between samples (no hardware averaging), the input pin has time to recover, even with the 3.3MΩ source.

This explanation makes sense out of more of the data than just the low-frequency behavior—it also explains the further downturn in the response for 32× averaging at the high end of the sampling rates checked.  At those sampling frequencies, the interval between bursts of 32 samples gets short enough that the input pin can’t recover even in the time between bursts.

The bottom line here is that the input to the ADC pins can only be modeled as a simple impedance if the source impedance is low enough that the noise stuck on the input line by the sampling is eliminated before the next sample is taken.  Obviously, 3.3MΩ is much too large a source impedance for use with PteroDAQ.  But how big a source impedance can I use and expect reasonable results?  More experimentation is needed.

Also, I might want to add an option to PteroDAQ to allow increased sample times for higher impedance sources.  The current 4-cycle sample time could be increased to 6, 8, 10, 12, 16, 18, 24, or 26 clocks (that is, up to about 3.8µs), allowing about 6–7 times higher source impedance than currently accepted, at some loss of conversion speed.

## 2015 July 21

### Measuring PteroDAQ KL25Z input impedance

In a series of posts (most recently Measuring BitScope BS-10 input impedance), I’ve been measuring the input impedance of my various ways of measuring AC voltage:

meter Z
DT-830B 0.42MΩ || 31.59pF
DT-9205A 13MΩ || 22pF
BitScope BS-10 oscilloscope 1.025MΩ || 9.8pF

I spent yesterday trying to add the PteroDAQ data acquisition system with the Freedom KL25Z board to that list.

One problem was that PteroDAQ was not designed to report an RMS voltage, but just a waveform, so I modified PteroDAQ to report the mean and standard deviation of a channel (not in the released version yet, as I still have some work to do on the user interface). Note that the mean of a channel is its DC bias, and the standard deviation is the RMS AC voltage. (I’ve never much cared for meters that report RMS AC+DC, which is the root-mean-square voltage without separating AC and DC components.)

A bigger problem is that PteroDAQ can only sample at fairly low frequencies, but the parallel capacitance is expected to be fairly small (pin capacitance for the pin is only about 7pF and the short wiring on the board should only add another couple of picofarads), so the RC time constants will be small. The result is that the low frequencies below the Nyquist frequency will not be much affected by the parallel capacitance, and all I would be able to estimate is the DC resistance of the inputs.

I can take advantage of a trick, however, to get effectively much higher sampling rates: aliasing. Because the input is a sine wave of stable frequency, f, I can sample it at every $\frac{n+\phi}{f}$ seconds and get a waveform that advances by phase $\phi$. I can pick the integer n to be large enough to get a feasible sampling rate while still seeing the whole waveform, especially if I pick the phase advance to be about $\phi=\pi/128$, so that I see all the 256 entries in the function generator’s table.

This trick has the further advantage of presenting the sample-and-hold with about the same value as it sampled on the previous sample, so that I don’t have to worry about the short sampling time not getting fully charged through a high-impedance input.  If I don’t do the aliasing trick, then the short sample time PteroDAQ uses (4 cycles of a 6MHz clock, or 667ns) is not enough to charge the sampling capacitor to the final voltage.

At higher frequencies, even this short sampling time is too long—at 1MHz the voltage changes substantially in 667ns, and the sampling capacitor ends up averaging the value over the sampling interval, which reduces the AC RMS voltage.

I made my measurements with the hardware averaging set to 1×, since averaging multiple readings is a digital low-pass filter that would hide the analog low-pass filter I’m trying to measure.  Because the measurements at 1× are so noisy, I took a large number of  measurements to determine the mean and standard deviation.  The results are still a bit noisy, as I did not realize the importance of having very precise sampling rates initially—if the $\phi$ value is too small, then I have to be careful to include an integer number of periods of the aliased waveform in the averaging to avoid bias, and if it is too large, then the short sample time is not long enough to charge fully and my waveform is not full scale.  A good compromise seems to be to pick n so that the sampling rate is around 5kHz and $\phi=\pi/128$ to get about a 19.5Hz aliased waveform. Only a few of my measurements were done with these settings, so I should probably redo the whole set at some point.

The aliasing trick is not a perfect one—at high frequencies there are a lot of glitches, where it is clear that the sampling did not happen at precisely the place in the waveform desired. This is probably due to jitter in the digital phase oscillators used in FG085, as the PteroDAQ interrupts should come at precise intervals (though the intervals may not be at exactly the frequency desired). The noise is much more of a problem with a high impedance source, as it may take several samples for the sampling capacitor to get back to the correct value.

I measured PTB0 with 1× sampling both directly driven by the FG085 (with 2.9Vpp and +1.8V offset) and through a 100.1kΩ resistor.

The dropoff in voltages at high frequencies with not series resistor is probably due to the averaging of the 667ns sampling time.

The impedance estimate derived from these measurements is pretty solid on the DC resistance, but the parallel capacitance estimate varies depending on how much of the high-frequency measurement I use in the fitting.

My estimate of C is 8pF±2pF, depending on how much of the high frequency data I include in the fit.

Estimating the input impedance of the single-ended pins of KL25Z at 2.5MΩ || 8pF seems pretty good. I’ll have to check the differential inputs separately, as there is no reason to suppose that they have the same input impedance.

I think that the 8pF I’m seeing is mainly the pin capacitance of the PTB0 pin, with a little extra board capacitance. The sampling capacitor is not really measurable here, since it is only connected to the input for very short intervals. To measure the RC time constant of the sample-and-hold circuit, we’d have to vary the sampling time (which is possible on the KL25Z, but which PteroDAQ is not set up to do).

## 2015 May 23

### Interesting observation with PteroDAQ

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 19:35
Tags: , , ,

In the lab reports on the optical pulse monitor lab, one pair of students made an interesting observation: the DC offset of the signal they were observing with the PteroDAQ data acquisition system seemed to be periodic with a period of about 46 seconds. In the electronics course, they learn early on about aliasing, because we usually sample our signals at 10Hz, 15Hz, 20Hz, 30Hz, or 60Hz so that the AC noise picked up and amplified can be aliased to DC and result in a DC offset, rather than making a mess of our signals.  There is a large 60Hz interference in the pulse-monitor lab, as students are generally doing transimpedance amplifiers with a total gain of around 100MΩ, so 10nA of stray current at the input results in a 1V output signal.  The aliasing trick gets rid of that 60Hz signal in the output, as long as the amplifier is not clipping as a result of the interference.

They attributed the periodic offset to slight errors in the 20Hz or 30Hz sampling frequency, so that the 60Hz interference was not being completely canceled, but was being aliased to 0.022Hz.  They did not have a very long recording, so I was not sure whether their explanation was correct—it was plausible, but so was random drift, and I wanted more evidence.

So I set up my own amplifier picking up 60Hz line noise in my house, and I did my own recording at 30Hz:

This waveform looks like a time-reversed and slowed down version of the signal I saw on the oscilloscope.

Sure enough, there is clear evidence of aliasing. The period is about 93.7s. That would be an error of having 1 sample too few every 2811 samples, an error of 356 parts per million. That would be a huge error for the crystal-controlled timer on the KL25Z board (the ABM3B crystal on the FRDM KL25Z board has a ±50ppm error or better—the ABM3B F3C marking does not correspond to the part numbers on the ABM3B datasheet, so it is possible that the F3C codes for a tighter spec). I also considered a software error, setting the counts wrong for the interrupt timer. It is unlikely to be an off-by-one error in the programming, though, since the number of counts with the prescaling of the timer should be 8333 (not near 2811), and the separate timer that reports the intervals is not showing any drift in the timing of the interrupts. So I think that the PteroDAQ is doing 30Hz sampling too accurately to explain the aliasing, if the line frequency is really 60Hz.

The beat frequency is about 0.0107Hz, which would correspond to the 60Hz line frequency actually being around 59.9893Hz (a bit too slow, so that we sample slightly earlier in each period, to get the time reversal). Is that in spec for the power grid? According to “Legal and Technical Measurement Requirements for Time and Frequency” by Michael A. Lombardi  [Measure 1(3):60–69  Sept 2006, http://tf.nist.gov/timefreq/general/pdf/2125.pdf],

The 60 Hz frequency delivered to consumers is sometimes used as the resonator for low-priced electric clocks and timers that lack quartz oscillators. The legally allowable tolerance for the 60 Hz frequency is only ±0.02 Hz, or 0.033 % [17], but under normal operating conditions the actual tolerance is much tighter.

So being off by 0.01Hz is within spec for the line frequency, but the 46s period that the students saw was out of spec, unless the frequency spec is for a long-term average and not for a window of only a few minutes.

Note that the ±50ppm for the KL25Z crystal is good enough for a lot of purposes (like USB signalling), but is not nearly as tight a tolerance as a digital wristwatch, which is typically ±6 ppm (there is no legal requirement in the US for wristwatch accuracy).  Of course, people who really care about the time use GPS, which has an accuracy of 6 parts per 1014 (in the satellite—the accuracy is considerably less by the time it gets to the receiver).

## 2014 June 4

### Random topics in class today

Filed under: Circuits course — gasstationwithoutpumps @ 19:20
Tags: , , , , ,

Since students have started on their last lab, there is no more material that I have to cover, so I threw today’s lecture open for questions.  I had prepared some material on Wien-bridge oscillators, in case no one had any questions, but we filled the time with stuff they were confused about from earlier in the quarter.  In roughly the order I covered them, we talked about

• FETs. I showed the cross-sections of nFETs and pFETs, explained the “back gate” or substrate connection and why it was tied to the source on the power FETs. I also talked about the flyback diodes and why they are needed when driving inductive loads.  This also gave me an opportunity to talk about how ignition coils on cars work.
• PWM. I redid a lecture that had not gone over well the first time, talking about how the rectangular voltage pulses turn into up and down ramps for current in an inductive load, and how duty cycle gets converted to current level.  I still think I could do a better job of the PWM talk, but the students were feeling better about understanding how their class-D amplifiers worked.
• I also introduced H-bridges for DC motor speed control, and showed how PWM could control the motor to turn forward or backward at different average current levels.
• A student asked about how the gain in theirpreamp affected thefinal output loudness, so I redrew a part of the comparator function from their lab handout:

Example of comparator output comparing a slow signal from a preamp and a fast triangle wave to get a pulse-width modulated wave.

I then showed how a small signal centered at the same voltage as the triangle wave would produce a 50% duty cycle, with only small fluctuations from 50% as the signal went up or down.

• Finally, I reviewed sampling and aliasing, explaining where the beat patterns they saw in their lab came from.  I think I need to provide more on that earlier in the quarter, as they did not seem to get as much from the sampling and aliasing lab as I had hoped.

Tomorrow is the last lab (unless students request extra time in the lab to redo something next week), and I expect all the students to finish their EKG soldering.  I did remember to suggest that everyone solder a board, so that they could have one to demo to people, but we’ll see how many takers there are tomorrow.

On Friday, I’ll once again take questions, but I’ll still have the Wien-bridge oscillator to present if they don’t have anything to ask.

Next Page »