In a series of posts (most recently More on measuring PteroDAQ KL25Z input impedance), I’ve been measuring the input impedance of my various ways of measuring AC voltage, and having some trouble getting a reasonable value for using the PteroDAQ as a measuring device. In the most recent post, I noted that hardware averaging seemed to make the measurements worse, not better, when the input impedance was high.

I decided to map out how bad this measurement error was, by changing the source resistance and seeing how the voltage measurement changed. I picked a low frequency (55Hz) with a high sampling rate (6001.5Hz), so that aliasing was not an issue.

My conjecture about the problem with the 32× averaging was that the KL25Z sample-and-hold circuitry was injecting interference onto the pin, and that too high a source impedance did not provide sufficient current to eliminate this noise before the next sampling of the pin.

I tried fixing the problem by adding a small capacitor between the pin being measured (PTE0) and ground. The idea is that the capacitor can short out the high-frequency interference, using charge from the capacitor to cancel the noise rather than from the source. If the capacitor is too large, then the low-pass RC filter of the source impedance and the capacitance will reduce the signal, but if it is too small, then the sample-and-hold will be confused by the noise from the previous sample. With the 55Hz signal and a 100kΩ source impedance, I tried a number of capacitors, looking for the one that would maximize the voltage reading with 32× hardware averaging. I settled on 470pF, which would give a corner frequency of 3.39kHz (approximately my Nyquist frequency).

With the 470pF capacitor, the source resistance can get as high as 100kΩ before the noise injection becomes a problem, when not using hardware averaging (at the 6kHz sampling rate—higher sampling rates would start seeing problems at lower impedances. In general, I think that sampling period should be at least 3.5 times the RC time constant of the source resistance and the added capacitance. For single-ended, 16-bit measurements with short sample times, the KL25Z hardware averaging has a period of 25 ADC clock cycles and PteroDAQ is set up to use a 6MHz ADC clock, so the samples are at 240kHz, which would suggest a maximum source impedance of 2.5kΩ for a 470pF capacitor using hardware averaging. This seems consistent with the measured data.

I realized this morning that I did not need to just conjecture the noise on the pin—I could stick an oscilloscope on it and measure it. I used a 47kΩ series resistor (so that the 1MΩ || 10pF load of the Bitscope oscilloscope would not make a huge difference) and a 10 Hz input from the FG085. I set the PteroDAQ sampling rate to 3750Hz, so that there would be about equal time for the 32 samples and for recovery between them. I captured single traces and got fairly consistent results. Here is an example:

The noise injected by the sample-and-hold circuitry is about 190mV peak-to-peak with the 47kΩ resistance, or about 4µA.

Adding the 470pF capacitor reduces the peak-to-peak noise to about 16mV or 340nA, but there is enough of a bias to the noise that the error is much larger, as seen by the slow decay back to the correct value in the following trace:

The injection of noise back into the circuit being tested is a particularly nasty property for test equipment to have. One could avoid it by adding a unity-gain buffer before the pin, which would have three good effects:

- The input impedance would now be the impedance of the op amp, which can be in the 10GΩ range (for the cheap MCP6004 op amps we use in class)
- If there was noise from the microprocessor, it would not be injected into the circuit being tested.
- The source impedance for the analog-to-digital converter would now be around 40Ω (for the MCP6004 op amps), so all these noise problems would go away.

There is one downside to using a unity-gain buffer: you get some non-linearity near the power rails, so the range of useful operation is reduced somewhat.

So when using the PteroDAQ, it is important to pay attention to the source impedance. When the source impedance, R, is high, one can either

- add capacitance to reduce the switching noise of the sample-and-hold circuitry (resulting in an RC time constant >3.5 times the sampling period, which can be user-specified (no averaging), 4.1667µs (single-ended channels), or 5.6667µs (differential channels) on the KL25Z; or
- add a unity-gain buffer to separate the input from the pin.

The noise consideration is a bigger constraint on operation than the input impedance of the analog-to-digital converter pins, which made my attempts to characterize the input impedance somewhat quixotic.