I have a huge stack of grading to do this weekend (about 20 new design reports and about 30 redone reports from earlier labs). I was rather disappointed with the reports for the class-D amplifiers, not because the amplifiers didn’t work (they mostly did), but because about 80% of the class is getting a REDO for errors in their schematics, which means I’ll be having to grade the reports again. I consider 20% REDO an acceptable level, but not 80%.
The most common error in the schematics was one that I had seen a fair amount in previous years: getting the source and drain of the pFETs swapped. It is a fairly serious error, as putting the transistors in backwards would cause a lot of shoot-through current from the body diode conducting. Students were wiring their transistors correctly (after some false starts), but documenting their designs wrong. A number of students also used the depletion-mode instead of enhancement-mode FET symbol, but I consider this a much less serious error (as long as they included the right part number), and would not have triggered an automatic redo for that mistake.
I warned the students about the source and drain orientation repeatedly, both as a class and (in many cases) individually. I was very careful to point out the convention for the source and drain notation in class and in the book, and they had it on their data sheets as well. I don’t know what else I can do, other than instituting in-class quizzes, which I may have to do next year.
There were a number of other documentation problems in the reports this week:
- Using their loudspeaker models, but not including the model in the report. In many cases, it was clear from their plots that they had screwed up the model somehow, but without any formulas or parameter values, it was impossible to figure out what they had screwed up.
- Oscilloscope pictures that did not say what the probes were connected to, or had incorrect labeling of the probes. This was mainly really bad lab technique, where they failed to write down what they were doing, and couldn’t reconstruct it from their memories. That is one aspect of the labs that I’ve not put much emphasis on this year—writing down what they are doing as they do it. I may have to emphasize that more next year, especially since the labs will be broken up into 4 95-minute sections instead of 2 3-hour sections, which will make memory even more unreliable.
- Not reporting the PWM frequency.
- Not remembering to include their bypass capacitors in their schematics. Some students may not have had bypass capacitors, though it was very difficult to get the amplifiers to work without them, as the H-bridge dumps a lot of high-frequency energy into the power lines, which gets coupled back to the comparator and the preamp.
- Generally bad copy editing. The spelling and grammar problems in some reports are just common non-native problems with articles, plurals, and verb tense, but a lot of the reports had huge numbers of spelling errors, duplicate words, missing words, comma problems, and incomplete sentences. I’ll be addressing this problem next year by giving students a bit more time to complete the reports (though that didn’t seem to help on the one report that students had more time on this year).