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2015 September 25

Teensy 3.2 available

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 08:22
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A new board in the Teensy series, the Teensy 3.2, has just been released.  It is almost identical to the Teensy 3.1, but has a better 3.3V regulator, so that more 3.3V power can be used by peripherals.  We’ll have to make some tiny changes to the PteroDAQ data acquisition system so that it will recognize the Teensy 3.2, but nothing major, as it will use exactly the same code as the Teensy 3.1.  I’ll have to reinstall the Teensyduino development system and find out how (or whether) it distinguishes between the boards.

(Update 2015-Sept-19:00:  The Teensyduino software treats the Teensy 3.1 and Teensy 3.2 identically, so there is nothing that needs to be done to PteroDAQ but to change some info items to be “3.1/3.2” instead of “3.1”.)

The addition of the voltage regulator is a substantial improvement to the board, allowing about 500mA of current on the 3.3V line, rather than the 100mA limit of the Teensy 3.1.

I still think I’ll recommend the Teensy LC for the electronics class, as a somewhat better price/performance ratio for the needs of the class, but the Teensy 3.2 is a good choice if you need a little more processing speed or the more complex DMA capabilities.

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2015 August 28

DMA counter for event counting on Freescale Kinetis processors

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 18:25
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The application note mentioned in PteroDAQ frequency channels is Freescale’s AN5083Using DMA for pulse counting on Kinetis, which I finally got around to looking up and reading today, after implementing frequency channels on the KL26, KL25, and K20 processors (Teensy LC, FRDM-KL25Z, and Teensy 3.1 boards, respectively).  The reason I looked it up finally was to look for a workaround for the biggest problem—namely that the CITER counter on the K20 has a maximum of 32767.  If I’m counting at the highest frequency (supposedly 8MHz or 6.26MHz, depending which documentation I believe, but I’ve not been able to get measurements much above 4MHz), that requires sampling at 125–245Hz or faster. But I often want to sample at factors of 60Hz, to alias out any frequency modulation from line interference.  The cruder DMA systems of the KL25 and KL26 use a 20-bit counter, and should be able to count to 4-5MHz (though they are likely to top out at 3MHz), so I could sample as slowly as once every 3.8s, even at the highest measurable input frequency.

I had no problem getting the counting to work with the 15-bit DMA_TCD_CITER counter. I can live with the 32767 count limit (at 60Hz sampling, that would be a 1.966MHz limit on the counting), but I wanted to see if I could use the optional interrupt that can be set up when the CITER counter ends to increment a software counter and reset the DMA counting.  That should give me an arbitrarily wide counter, at the cost of perhaps missing a count at the wraparound (an error of 30.5ppm, about the same as the clock error).

Unfortunately, AN5083 merely explains what I had already figured out for myself—without even the essential warning that you need a NOP after disabling the DMAMUX before looking at the counter to avoid a race condition on the KL25 and KL26:

    (&DMAMUX0_CHCFG0)[0] &= ~(DMAMUX_ENABLE);       // turn off at DMAMUX
    __asm__ volatile( "nop" );
    uint32_t count = 0xfffff - (DMA_DSR_BCR0 & 0xfffff);

They only say

The major loop counter of the DMA register DMA_TCDn_CITER_ELINKNO is limited to 15 bits, in the case where the channel linking feature of the DMA is not in use (refer to DMA chapter in the Reference Manual). Therefore, there is a limitation of 32K major loops count. So, user must check CITER register and make sure it will not reach to zero. If, CITER reaches zero, BITER will reload the value from BITER register.

I tried for a good chunk of yesterday to get the code working with the interrupt.  I can get the interrupt to occur (detected by turning off an LED in the interrupt return), I can read the longer frequency counter (detected by turning off an LED if the count to return is >32767), and the count is returned to be pushed on the queue, but something gets wedged and that longer count is never output to the host.

The processor needs to be power-cycled, the same as if the processor had gone into an infinite loop (which is what the Teensyduino unimplemented_isr routine does). I did disable the DMA error interrupt routine (with DMA_CEEI), so that isn’t the problem.  I even confirmed this by enabling the error interrupt and providing a dma_error_isr routine that turns off the LED, but the LED did not turn off.  I also checked the DMA_ES register at the beginning and end of the dma_ch0_isr routine and in the routine that reads the counter, and DMA_ES was always 0.  So if there is an error, it is not being reported by the hardware.

I suppose that an SWD debugging interface (not available on the Teensy 3.1 board) might be useful here, as I could at least check my conjecture that the processor is looping in the fault_isr routine.  It may be wedged somewhere else.  And there is always the possibility that there is an undocumented hardware bug (like the race condition between DMAMUX disabling and reading DMA_DSR_BCR on the KL26) that requires some workaround that I haven’t thought of yet.

I’ve given up on the higher resolution counters for Teensy 3.1 for now and just pushed the 15-bit implementation (with the interrupt code mostly commented out) to the BitBucket PteroDAQ repository.  If anyone reading this blog is familiar with the DMA interrupts on the K20 processor, please look at the code in kinetis_frequency.c and tell me what I’m doing wrong!

2015 August 25

PteroDAQ frequency channels on FRDM-KL25Z

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 23:53
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In PteroDAQ frequency channels I said

The next step for me is to implement frequency channels for the FRDM-KL25Z board (pretty much identical to the KL26 on the Teensy LC, except for having to use the MBED syntax for the register setting rather than the one Teensyduino uses) and the Teensy 3.1 board (the K20 DMA is much more complicated, so it will probably take me a while to figure out and set up—especially if it also has undocumented race conditions). Once I get those working, I’ll have to figure out how to do the GUI so that people can quickly figure out that which combinations of frequency channels are legal. I’ll probably want to do that with separators in a menu, greying out sections that already have frequency channels in use.

I got about half of that done today.  I started out with how to grey out the frequency channels that were inaccessible (because another pin on that port was being used)—but doing that lead me to needing to list all the current channels, which was done in several different places already and was rather awkward.  From there I decided to clean up and refactor a lot of the GUI code, which had gotten rather long and confusing.

So most of the day was spent on refactoring the GUI, breaking it up into classes and getting rid of global variables.  I think that the GUI code is more maintainable  now, but there are still a few things that feel like they are in the wrong place in the code, so some stuff may move around a little in future releases.

After the refactoring, greying out the unavailable frequency pins was pretty easy, and I’m reasonably happy with the user interface for pin selection now, though I think I need a new icon for frequency measurement.  I have a period of a sine wave for analog channels, and a period of a square wave for digital channels, but I don’t have as obvious an icon for frequency channels.  (I was considering just a big “Hz”, but that would not look compatible with the sine and square wave icons.)

Adding frequency channels for the FRDM KL25Z board did not take long—the biggest trouble was converting the KL26 code for the Teensy LC into MBED’s format for accessing registers.  Just about everything else is the same (except that the KL25 has only 2 ports that can control the DMA counters: A and D, rather than the 3 (A, C, and D) of the KL26. I have pushed the code for the frequency channels up to the PteroDAQ site on BitBucket.

I don’t know whether I’ll get the Teensy 3.1 code done tomorrow—I have to go into the office for office hours and for the banana slug genomics meeting, and I need to start working on my biobibliography and teaching/research statements for my merit review.  They are due early in September, and I’ve not started on them yet.

I hope to have the frequency channels working on the Teensy 3.1 by the end of the week, so that I can rewrite the chapter of my book on the hysteresis oscillator, to use the frequency channels, rather than a separate frequency detecting program as I used for the last couple of years.

2015 August 24

PteroDAQ frequency channels

I’ve been trying to add frequency channels to PteroDAQ, so that it can plot the frequency of an input on a digital channel.  So far, I’ve only implemented this for the Teensy LC, which uses a KL26 ARM processor.  Because I want to be able to mix frequency channels with regular analog or digital channels, I’m using the method that counts rising edges in a fixed time period (the sampling period set for PteroDAQ), rather than timing how long there is between edges.  The chosen edge-counting method is more appropriate for high-frequency signals than for low-frequency ones, but by using long-term averaging, one can measure fairly low frequencies also.

In order to count adequately high frequencies, I need to run a hardware clock that does not use interrupts to do individual counts, but which can keep counting why the processor does useful stuff.  One choice (made, for example in the Teensy FreqCount library) is to use the low-power timer LPTMR.  But only one pin on the Teensy LC can be used with this timer—pin 13, which is also the LED output pin.  I wanted something more versatile, that could be used with any digital pin and that could have multiple frequencies being counted at once.

The closest I’ve been able to come so far is to use the DMA channels as counters (a suggestion my son made to me, based on ideas he saw in a Freescale application note).  I can use any pin on Port A, C, or D to control a DMA channel, and there are 4 DMA channels, but each port only provides one signal to the DMA, so I can have 3 independent frequency measurements (one for any pin from Port A, one for any pin from Port C, one for any pin from Port D).  If I use the same trick on the Teensy 3.1, which is a K20 processor, I can have 5 independent measurements, one each from Ports A, B, C, D, and E.  On the FRDM-KL25Z board, I only get 2 measurements, one each from Ports A and D.

To use the DMA channel as a counter, I had to set it up with a large byte count (the max is 0xFFFFF, or 1,048,575) and have the DMA do a no-op 1-byte transfer from a fixed source to a fixed destination on each external signal. On each read of the frequency, I read the remaining count and subtracted from 0xFFFFF to see how many external signals had happened, and put that count in the queue for sending to the host computer like any analog read.

It took me a long time to get the code working on the Teensy LC (about 2 days).  The first problem was just understanding all the pieces of the DMA system:

  • Using the SIM_SCGC6 and SIM_SCGC7 registers to turn on clocking to the DMAMUX and DMA
  • Using DMAMUX0_CHCFGn to route signals from the ports to the DMA channels
  • Setting up the PORTx_PCRn register to send DMA signals on rising edges
  • Setting up the DMA_SAR, DMA_DAR, DMA_DSR_BCR, and DMA_DCR registers for the DMA operation itself.

Another big chunk of time was spent rearranging some of the python software, so that the frequency channels could be selected in the GUI and the communications protocol to the microcontroller board updated to handle frequency channels.

But the biggest chunk of time was spent trying to debug a race condition.  No matter what I did, running a high-frequency signal with a high sampling rate resulted in things failing in unpredictable ways after an unpredictable delay (the counts all coming out 0, the communication packets getting incorrect checksums, or just freezing).  I had to power cycle the Teensy LC after each failure to try again.

I tried all sorts of debugging tricks (no SWD debugging interface on the Teensy LC), including sending contents of the various DMA registers instead of the count, to see which things were going wrong.  Unfortunately, almost everything seemed ok until it failed, and then nothing came out.  I was convinced it was a race condition—but where?

I tried various ways of turning the counting on and off, based on different suggestions in different Freescale manuals (using the ERQ bit in DMA_DCR or using the ENABLE bit in DMAMUX).  I even tried various combinations of the turning on and turning off in different orders.  It was clear to me that the problem was in reading or resetting the DMA_DSR_BCR register, but there were several places where a race might be occurring and no help in any of the reference manuals.

By trial and error, I finally figured out that if I used the DMAMUX enable bit to turn off the counting, and put a NOP after it before looking at the DMA_DSR_BCR register, the race condition went away.  The crucial problem seems to be that looking at DMA_DSR_BCR at the same time that hardware is trying to change it results in unpredictable behavior—not just unpredictable values for the read, but seriously wedging the DMA so that a hardware reset is needed.  The extra NOP makes sure that any pending DMA operations are completed before accessing the DMA_DSR_BCR register.  This warning does not seem to be present in any of the KL26 documentation—I’m not sure the engineers who designed the DMA were aware of it.  Either that or the engineers failed to communicate the importance of this constraint to the tech writers who did a sloppy cut-and-paste job in writing the KL26 DMA documentation (for example, there are references to a non-existent “TCDn”, by which they mean the 4 registers DMA_SARn, DMA_DARn, DMA_DSR_BCRn, and DMA_DCRn).

Running the frequency channel with a square-wave input from the FG085 function generator lead to some more discoveries:

  • The samples taken by PteroDAQ have a fairly large amount of jitter at high sampling frequencies.  At 10kHz sampling and a 500kHz input, the number of observed edges varied from about 47 to 53, representing a ±6µs variation on the nominal 100µs.  My son suggested that the jitter was caused by the USB communications—if the timer interrupt occurred while the USB interrupt was in progress, the sample would be delayed up to about 6µs, and this could happen about every millisecond with heavy communication. Sure enough, the long periods were followed immediately by short periods, and some clusters about 1msec apart occurred (though not ever millisecond).  At low sampling frequencies, there is less USB communication, so a lower probability of getting the 6µs delay, which also represents a much small fraction of the period, so I did not see jitter at lower sampling frequencies.
  • One of the clocks is out of spec.  When the FG085 was putting out a nominal 500kHz signal, the PteroDAQ system measured it at 499958.5 Hz, which is –83ppm.  The two crystals should each be about ±20ppm, so an 83ppm discrepancy is larger than expected. With a nominal 5kHZ signal, the PteroDAQ system measured it at 4999.524 Hz (–95ppm).  I’ll have to take the function generator and PteroDAQ board into the circuits lab and use the frequency counters and function generators there to see what the actual accuracies are.  For anything that we do in the applied electronics class, 100ppm is good enough, but it would be nice to know how far off my instruments really are.
  • The FG085 glitches (turning off the output for a while) when changing frequency.  I plotted the frequency as I stepped the frequency down in 100Hz steps from 5kHz to 2kHz:
Each time I turned the knob, the FG085 turned off the output for a while, resulting in a large number of missing counts.

Each time I turned the knob, the FG085 turned off the output for a while, resulting in a large number of missing counts.

The next step for me is to implement frequency channels for the FRDM-KL25Z board (pretty much identical to the KL26 on the Teensy LC, except for having to use the MBED syntax for the register setting rather than the one Teensyduino uses) and the Teensy 3.1 board (the K20 DMA is much more complicated, so it will probably take me a while to figure out and set up—especially if it also has undocumented race conditions). Once I get those working, I’ll have to figure out how to do the GUI so that people can quickly figure out that which combinations of frequency channels are legal. I’ll probably want to do that with separators in a menu, greying out sections that already have frequency channels in use.

Once all that is done (later this week??), I’ll push it up to the PteroDAQ repository.

2015 August 16

Teensy LC support for PteroDAQ working

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 09:08
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Despite what I claimed in Teensy LC support for PteroDAQ written but not tested, adding support for the Teensy LC board to the PteroDAQ data acquisition system also took a day of effort, not just a couple of hours.  The board arrived in Saturday’s mail, so I tested the code immediately. My initial attempt did not work, and debugging took an embarrassingly long time.

The first problem was that the KL25Z code had used the SysTick timer to do the interrupts for the periodic sampling, but the Teensyduino usb_serial code uses the SysTick timer for other timing purposes (it uses SysTick as a timestamp).  On the Teensy 3.1, I’d used one PIT (periodic interrupt timer) for the periodic sampling, and two others for keeping a high-resolution timestamp, but the Teensy LC does not have that many PITs.

I ended up using the LPTMR (low-power timer) for the sampling frequency, which gives a wide range of frequencies with the precaler (allowing a very long sample period of 268s).  Unfortunately, the LPTMR is only a 16-bit counter, so the resolution of frequency is not great—about 15ppm at low frequencies (with counter values between 32k and 64k), and period step sizes of 62.5nsec at sampling frequencies above 244Hz.  I can’t hit 60Hz exactly, but the 10ppm that it is off is less than the error of the crystal oscillator and far less than the error of the line frequency of the power lines.

Getting the LPTMR to work correctly took a long time, mainly because of spelling errors (sometimes the name needed is LPTMR, sometimes LPTIMER, sometimes LPTMR0).  The inconsistency seems to come mainly from the kinetis.h file provided in the Teensyduino code.

The SysTick timer we used on FRDM KL25Z implementation is a 24-bit counter running at 48MHz, so it has a resolution of  20.83 nsec for frequencies above 0.35Hz, and 333nsec at lower frequencies. The Arduino implementations use the same timer for both timestamps or periodic interrupts (which I could also have done on the Teensy LC, using the same pair of PITs for either) since the timestamps are not used directly with periodic interrupts.

I looked at the size of the different implementations of the firmware for PteroDAQ with the current implementations as well as the longest sampling periods:

board bytes longest period
Teensy 3.1 12,536 119.3046 s
Teensy LC 12,632 268.4355 s
FRDM KL25Z 26.6k 5.592405 s
Arduino Leonardo 9,908 4.194240 s
Arduino Uno 7,350 4.194240 s

The Teensy 3.1 implementation could easily be modified to get ridiculously long sample times, as there is a spare 32-bit PIT to get times up to 512Gs (over 16000 years) with a resolution of 27.8ns, but the other implementations would be harder to change.  Using the 2-PIT approach on the Teensy LC or the FRDM KL25Z could easily get up to 384Gs, with a resolution of 41.7ns.

I think I may switch all the ARM boards over to using 2 PITs for timing, for both the timestamps and for the periodic interrupts, as this seems to provide the best tradeoffs of period and resolution.

 

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