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2015 April 27

Ideas for improving hysteresis lab

Filed under: Circuits course — gasstationwithoutpumps @ 08:38
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The hysteresis lab was the least successful one so far this year.  Students got the designs done and built, but they learned less than they could have from the lab (too much copying of “answers” without understanding) and the lab took too long for the time allotted.

I’m considering going back to a 2-day hysteresis lab, but expanding the lab slightly to include using an nFET to control a loudspeaker (probably with a series resistor to limit current to 500mA). Adding the nFET as a low-side switch would be a useful thing for them to know about (it is a standard arrangement for controlling heating elements, solenoids, and other devices in lab equipment), and would prepare them better for the class-D power-amp lab.

The problem here is that a good oscillation frequency for a touch sensor uses a small capacitor (hence a high frequency), while a good oscillation frequency for the loudspeaker is much lower (200Hz–4kHz).  I can have them add an external capacitor (resulting in little or no touch sensitivity) when driving the loudspeaker, or I can have them build two oscillators: a high-frequency one and a low-frequency one.

I’d want to redesign the board they solder the hysteresis oscillator on to make room for the nFET and loudspeaker connections,  plus giving them more holes for connecting up unused pins on the 74HC14N chip.  This will probably make the board bigger than 2.5cm×5cm, raising the price by 50¢.  They’d need an extra nFET in their kits (another 40¢) and perhaps another screw terminal (80¢).  An extra buck or two for the parts is no big deal, as the lab fee is already larger than what the students are getting, though the extra cost for having to use UC-approved vendors may be eating up most of the “excess” fees.

The lab could be split between the breadboard and the soldering phases, with students who are behind still completing the breadboarding in the second lab.

One question I’ve not resolved is how to reschedule the labs so that there is room for a 2-day hysteresis lab.  Is there any lab that currently takes 2 days that can be squished to 1 day (with less damage than squishing the hysteresis lab)?  How do I keep the reports on schedule so that I can grade over the weekend?


2014 June 4

Random topics in class today

Filed under: Circuits course — gasstationwithoutpumps @ 19:20
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Since students have started on their last lab, there is no more material that I have to cover, so I threw today’s lecture open for questions.  I had prepared some material on Wien-bridge oscillators, in case no one had any questions, but we filled the time with stuff they were confused about from earlier in the quarter.  In roughly the order I covered them, we talked about

  • FETs. I showed the cross-sections of nFETs and pFETs, explained the “back gate” or substrate connection and why it was tied to the source on the power FETs. I also talked about the flyback diodes and why they are needed when driving inductive loads.  This also gave me an opportunity to talk about how ignition coils on cars work.
  • PWM. I redid a lecture that had not gone over well the first time, talking about how the rectangular voltage pulses turn into up and down ramps for current in an inductive load, and how duty cycle gets converted to current level.  I still think I could do a better job of the PWM talk, but the students were feeling better about understanding how their class-D amplifiers worked.
  • I also introduced H-bridges for DC motor speed control, and showed how PWM could control the motor to turn forward or backward at different average current levels.
  • A student asked about how the gain in theirpreamp affected thefinal output loudness, so I redrew a part of the comparator function from their lab handout:
    Example of comparator output comparing a slow signal from a preamp and a fast triangle wave to get a pulse-width modulated wave.

    Example of comparator output comparing a slow signal from a preamp and a fast triangle wave to get a pulse-width modulated wave.

    I then showed how a small signal centered at the same voltage as the triangle wave would produce a 50% duty cycle, with only small fluctuations from 50% as the signal went up or down.

  • Finally, I reviewed sampling and aliasing, explaining where the beat patterns they saw in their lab came from.  I think I need to provide more on that earlier in the quarter, as they did not seem to get as much from the sampling and aliasing lab as I had hoped.

Tomorrow is the last lab (unless students request extra time in the lab to redo something next week), and I expect all the students to finish their EKG soldering.  I did remember to suggest that everyone solder a board, so that they could have one to demo to people, but we’ll see how many takers there are tomorrow.

On Friday, I’ll once again take questions, but I’ll still have the Wien-bridge oscillator to present if they don’t have anything to ask.


2014 May 30

Class-D amplifier lab done, EKG block diagrams begun

Filed under: Circuits course — gasstationwithoutpumps @ 21:08
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Yesterday’s lab ran long (as expected), because students had not gotten enough done in Tuesday’s lab.  But everyone in the lab did get a working class-D power amplifier.  Several also managed to measure the turn on and turn off times for the comparators driving the FETs, though that required some hands-on guidance in using the digital scopes (setting the trigger level to the FET threshold voltage, then looking to see how long the rise or fall was before reaching the trigger level.  As expected, everyone had chosen values that made the pFETs turn on and off quickly, but it was difficult to get the nFETs to turn off quickly.  I don’t know whether anyone managed to equal turn on and turn off times for the nFET (they turned on fairly fast), but several groups managed to keep their FETs cool.  Even those with warm FETs did not dissipate so much in them that they got dangerously hot.

I’ll be reading the design reports over the weekend, and I’ll see whether the students really understood PWM or not.  I suspect that about half the groups understood what they were doing well enough, and the other half got part of the ideas.  There should be time on Monday to review the idea of PWM and to explain again why it is a good choice for efficient power delivery, particularly for inductive loads.

Today, I returned the quiz 2s redone as homework.  Students did fairly well on them as homework (range 18.5 to 31.5 out of 36, up from 7 to 17 on the timed quiz).  The biggest difficulty was with the last problem, which asked them to design a simple amplifier, giving both a block diagram and a schematic.  A lot of students did not understand the question as I phrased it, perhaps because I had not been clear enough earlier in the quarter about what a block diagram means and how to use it.

Students have not yet internalized the idea of something having inputs and outputs, and a block diagram being a refinement of an I/O spec into I/O specs for subunits.  I may need to use that language more explicitly earlier next year. I’m thinking also that I need to add more text to the lab handouts next year and refer to them as a draft textbook rather than as lab handouts.  How many pages do I have so far?

handout pages
01-thermistor  11
02-microphone  9
03-hysteresis  11
04-electrodes  7
05a-loudspeaker  8
03b-sampling  7
06-audio-amp  6
07-pulse-monitor  11
08-pressure-sensor  8
09-power-amp  13
09-power-amp-addendum  6
10-EKG  5
total  100

One hundred pages is a bit short for a textbook, but there is a lot of explanatory material still missing (most of which I provided in class or in lab). If I worked on it diligently over the summer, I could probably create a book with most of what the students need that would be around 200 pages. Do I have the energy to turn this into a textbook? Is it worth the effort?

After going over the block diagram of the quiz problem, I helped the students develop an EKG block diagram.They did get to the realization that the unknown but potentially large DC offset from the EKG electrode half cells limits the gain that they can ask from the first stage of the EKG, and that they’ll have to high-pass filter and add more gain.  The design is similar to their pressure sensor instrumentation amp, but the gain needs to be higher (1000 to 1500, rather than 100 to 250), and the pressure sensor amplifier had to go down to DC, so did not include a high-pass filter.

I was a little worried that I may have suggested too high a lower end for the passband (0.1Hz to 40Hz).  They’ll get less baseline drift with a 0.5Hz cutoff instead of 0.1Hz.  My EKG designs have used 0.05Hz—88.4Hz and 1.0Hz–7.2Hz for the blinky EKG.  Both worked ok, but I now think that the 7.2Hz cutoff is too low (it was adequate for blinking an LED, but not for recording the waveform).  Since I did not have much problem with a 0.05Hz corner frequency, I think they’ll be ok with a 0.1Hz one.  The blinky EKG circuit has an adjustable gain (needed to make the R spike large enough to light the LED), but it is probably better to have a fixed gain.

It would be really nice if they could finish the EKG on Tuesday, since the annual undergraduate poster symposium is scheduled for the same time as the Thursday lab, and I always like to spend an hour or so looking at the posters.

2014 May 24

Class-D amplifier lecture 2

Filed under: Circuits course — gasstationwithoutpumps @ 17:41
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Yesterday, in the last lecture before the long weekend (hence before they start wiring their Class-D power amplifiers), I covered three topics:

  • open-collector outputs.  I had hoped to avoid that this year by switching to the TLC3702 comparators, but I couldn’t get the TLC3702 comparators to work with the FETs, so I went back to using the LM2903 comparators that the students got in their parts kits.  Because I had already cut the open-collector information from the lab handout, I had to cover it in lecture, and I’ll have to write an addendum to the handout today.
  • LC filters for the loudspeaker.  This was a pretty rushed job.  I didn’t even have time to get them to derive the LC filter behavior with no load (the standard voltage divider formula \frac{Z_{down}}{Z_{up}+Z_{down}} becomes \frac{1/(j \omega C)}{j\omega L + 1/(j \omega C)}=\frac{1}{1-\omega^2 LC}, which goes to infinity at \omega=1/\sqrt{LC} and 0 at DC and infinite frequency.  Instead I pointed them to a gnuplot script that they needtomodify to see how much power the LC filter delivers to the loudspeaker at different frequencies, with different choices of capacitor (no choices for them on the inductor—it is a 220µH 0.252Ω AIUR-06-221 inductor).
    LC filter and loudspeaker model used for sizing the capacitor in the gnuplot script.  The students need to replace the loudspeaker model with the one that they created in an earlier lab.  I think that next year I may use a much simpler loudspeaker model in the script, so that I can tell whether the students have replaced the model or not.

    LC filter and loudspeaker model used for sizing the capacitor in the gnuplot script. The students need to replace the loudspeaker model with the one that they created in an earlier lab. I think that next year I may use a much simpler loudspeaker model in the script, so that I can tell whether the students have replaced the model or not.

    The output of the gnuplot script looks something like this:

    Output of the gnuplot script, note that too small a capacitor results in a spike near 61kHz, and nowhere near enough suppression of their 50kHz–100kHz PWM frequency. Too large a capacitor results in a big boost in gain around 3.8kHz, which would a different sort of problem.

    Output of the gnuplot script. Note that too small a capacitor results in a spike near 61kHz and nowhere near enough suppression of the 50kHz–100kHz PWM frequency. Too large a capacitor results in a big boost in gain around 3.8kHz, which would a different sort of problem. Click
    here for a PDF version of this plot.

  • Block diagram for the class-D amplifier.  I had originally planned to spend almost the entire lecture having the students develop the block diagram, but the addition of almost 45 minutes on open-collector outputs and review of the FET driver stage left me with little time for the block diagram. I did get some participation from the class in developing the diagram, but almost entirely from one student.  I felt bad about presenting, rather than getting them to participate in creating the block diagram, but they had to have a block diagram to do their more detailed design over the weekend.One important point I that I emphasized, based on common problems on the second quiz, is that a block diagram is not a simple pipeline, but can have merging and splitting.  The class-D amplifier has merging of voltage generators for DC bias with the signal path and merging of the triangle wave generator with the signal path.
    One good thing came out of the block diagram discussion: in putting together the design they had the output of the preamp centered at 3v but the input of the comparators centered a 0v.  I could point out that putting range information on the signal lines allowed them to catch this error early (before even doing the schematic).  Most of the class was able to come up with the standard solution for changing the C bias: adding a high-pass RC filter.  I don’t know whether they can choose a corner frequency appropriately, but we’ll see that on Tuesday.

I didn’t get a chance to teach them about real power, either, which the LC script computes.  I’ll have to go over that next Wednesday, between the two halves of the lab.  There is a writeup of the concept in the lab handout, but my experience has been that students in this class don’t learn from written material.

I’ve also told the students that they need to get all their required “REDO” assignments turned in by Wednesday.  It seems that this year’s class does not have the time-management skills to handle open deadlines—they keep putting off redoing the assignments.  Given that they sometimes don’t fix the assignments sufficiently when they turn them in again, leaving the assignments to the last week is really dangerous.  Next year I’ll have to make one-week deadlines for redoing the assignments, though I can be generous about extending deadlines on request.

Overall, the lecture was way too rushed, because of the extra coverage needed for open collectors. Next year I’ll have to make sure to allow 3 lectures for the class-D power amp, which means not having it on the week with Memorial Day.  I’ll probably want to move Quiz 2 a little earlier also, so that it isn’t the week before the class-D power amp.

2014 May 22

Class-D lab revision didn’t work

In Long weekend, I discussed what I was planning to do about anticipated problems with the class-D amplifier lab, specifically

  • Replace the AOI518 nFET with one that has a lower input capacitance, such as the PSMN022-30PL,127.  The gate charge at VGS of 4.5v is 4.4nC, about half that of the AOI518.
  • Replace the open-collector comparator with one that has push-pull output, like the TLC3072, which can provide ±20mA current (more than the LM2903, even before we allow for the current through the pullup resistor).

I did a neat version of the schematics last night using the TLC3072 comparators and the AOI518 nFET. This year I remembered to include an adjustable gain stage in the preamp, so that I could more easily control the volume. Today in the lab, while the students were soldering up their instrumentation amps for the pressure sensor, I wired up the class-D amplifier, one stage at a time, confirming that each stage worked using the oscilloscope before moving on to the next. The build took me longer than I had expected—almost 2 hours.

Everything worked fine until I connected the drains of the two FETs together.  Initially it worked ok, but after about 20 seconds the shoot-through current increased, causing the current limitation of the bench power supply to kick in.  Then the voltage on the lower power rail moved up  close to ground, and the input voltage on the comparator was swinging below the negative rail.  I think that this damaged a couple of my TLC3072 chips—I’ve marked them, and I’ll have to test them before using them.

Replacing the AOI518 transistor with the smaller  PSMN022-30PL,127 did not help.

I finally borrowed an LM2093P chip from one of the students (I’d left mine at home, by mistake) and tried replacing the TLC3072 chip with the LM2093P. They have the same pinout, but the LM2093P is an open-collector output, so I had to add pullup resistors.  I guessed a couple of values, based on vague recollections of last year’s design, and the amplifier worked.

Initially I could only run the amplifier up to ±7v on the power supply, without the FETs getting too warm—there was still too much shoot-through current during transitions.  I switched to a lower resistance for the pullup on the pFET gate, to make the voltage swing less and the turn-off faster.  At that point the amplifier worked quite happily with a ±8v swing without the transistors getting warm.The circuit worked with either of the nFET transistors, so I’ll just have the students stick with the AOI518 in their parts kit.

I couldn’t crank up the volume on the speaker, though, because I got feedback squeal whenever the gain got too high.  Perhaps I should make a long speaker extension cable for students to do testing next week.  I seem to be out of speaker wire, though.

The class-D amplifier design will be a tough one for the students, and I’ll need to do a supplemental handout on open-collector outputs (I’d cut that material from the handout when I thought that we would be using the TLC3072 comparators).

Last week I thought that the students could start on the class-D amplifier in lab today, having finished the soldering for the pressure-sensor amp on Tuesday, but it took almost the whole lab time today for students to finish the soldering, even though everyone had working breadboards on Tuesday.  The lab ran over by almost 2 hours for one group, taking a total of 8 hours instead of 6 (last year the same lab took only 4 hours for the slowest group, probably because last year’s class came to lab more prepared).

The layout took longer than students expected, as did the soldering.  Everyone did (eventually) get working soldered instrumentation amps, though for a couple of groups I had to point out that their wiring did not match their schematic (they had called me over to help debugging).

In one case they had connected a resistor to the wrong point in their circuit.  I found the bug by tracing where their virtual ground was connected, and asking them to identify each component. Even after I showed them both resistors connected to their virtual ground, where only one was supposed to be, it took them a long time to realize what the discrepancy was. They had wired exactly what they had laid out, but the bug was in their layout, and they had not done a thorough enough job of checking against their schematic.

Another group had a working circuit but with too little gain. After checking a few of the DC voltage levels with them, I compared each of their resistors to the schematic.  In one place they had wired in a 1kΩ resistor where the schematic called for a 10kΩ resistor.  They unsoldered the incorrect resistor and soldered in the resistor from the design, which salvaged the circuit.

I also returned Wednesday’s quiz in lab today—pretty much like last year, the scores were much better on the second quiz than the first one, though still only half what I think the students should be able to do at this point of the quarter.  I’m once again assigning the students to redo the quiz as homework.  I need to decide soon whether to give them another quiz during the final exam time.

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