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2017 April 10

Electret microphone hysteresis

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 09:05
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In attempting to determine the I-vs-V characteristics of an electret microphone, I stumbled across a phenomenon that I’m still having difficulty explaining.  What I was looking for was a plot like this one:

I-vs-V DC characteristics for an electret microphone. The linear and saturation regions are nicely distinguished and there is little noise.

In previous years I had collected the data with PteroDAQ, but this plot was done with my Analog Discovery 2, which combines both the function generator and the data acquisition. Because I was in a bit of a hurry, the first time I tried doing the characterization, I used a shorter period for the function generator, and got a somewhat different plot:

The hysteresis observed here was unexpected. The loop is traced clockwise, with the upper curve for increasing voltage and the lower curve for decreasing voltage.

At first I thought that the effect was a thermal one, like I saw when characterizing power MOSFETs, but a thermal phenomenon would get more pronounced at slower sweep rates (more time to heat up and cool down), while the hysteresis here could be reduced by sweeping very slowly. Also, the hysteresis did not rely on running large currents—the mic was dissipating less than 1mW at the most, and changing the voltage range did not change the hysteresis much.

My next conjecture was a capacitive effect, which I tentatively confirmed by either adding a capacitor in parallel with mic (increasing the hysteresis) or a capacitor in parallel with the 5.1kΩ sense resistor (which reduced the hysteresis or even reversed it).

I tried playing with the frequency of the excitation waveform, to see what happened to the hysteresis:

This pretty plot shows the transition from nearly DC (the curve that looks like the first one of the post) to something that looks almost like a resistor, with current going up linearly with voltage, as the frequency is increased.

Because the hysteresis did not seem to depend on the amount of the sweep, I picked a voltage well into the saturation region (4V), and tried doing a Bode plot of impedance for the mic for a relatively small signal (±1V). I then fit the Bode plot with an (R1+C)||R2 model:

The parallel resistor corresponds to the slope of the DC I-vs-V curve around a bias of 4V. The model fits the data so well that the curve for the data is hidden by the model curve.

I also tried a Bode plot for a DC offset of 2V and an amplitude of ±300mV:

Like with the 4V DC bias, I got an extremely good fit with the (R1+C)||R2 model. The parallel resistance is different, because the slope of the I-vs-V plot is a little higher (so smaller resistance) at 2V than at 4V.

Because the network tool in WaveForms 2015 provides phase information as well as magnitude information, I did my fit first on magnitude, then on phase. The phase fitting was also extremely good:

I show only the 2V phase plot here—the 4V one is similar, though the biggest phase shift is -56.5° at 3.5V, rather than -45.1° at 4.6 Hz.

So I have an excellent electrical model of the behavior of the electret mic at a couple of different bias voltages, with a simple explanation for one of the parameters of the model. I’m still mystified where the capacitance (about 1.7µF) and the other resistance (about 8kΩ) come from. I suppose, theoretically, that they could be tiny surface mount components inside the can of the mic, but I see no reason for the manufacturer to go to the trouble and expense of doing that. The pictures of a disassembled mic at suggest a rather low-tech, price-sensitive manufacturing process.

Incidentally, until I looked at those pictures, I had a rather different mental model of how the electret mic was assembled, envisioning one with a simple membrane and the electret on the gate of a MOSFET. It seems that the electret is put on the surface of the membrane and a jFET is used rather than a MOSFET. After thinking about it for a while, I believe that a jFET is used in order to take advantage of the slight leakage current to the gate—the gate will be properly biased as a result of the leakage. The OpenMusicLabs post showed a 2SK596 jFET (an obsolete part), which has an input resistance of only 25—35MΩ, easily low enough to provide bias due to leakage currents. If the gate is biased to be about 0V relative to the source, then the jFET is on by default,

The 1.7µF capacitance is huge—many orders of magnitude larger than I could explain by a Miller effect (unless I’ve screwed up my computations totally) as all the capacitances for the jFET are in the pF range, and the multiplier for the Miller effect should only be around 5–50 (1–10mS times the 5.1kΩ load), so I’m still at a loss to explain the hysteresis. I checked to see whether the effect was something in my test setup, by replacing the mic with a 10kΩ resistor, but it behaved like a 10kΩ resistor across the full range of frequencies that I used for testing the mic—this is not some weird artifact of the test setup, but a phenomenon of the microphone (and probably just of the jFET in the mic).

I suppose I should buy a jFET (maybe a J113, that has a 2mA saturation current with a 0V Vgs) to see if other jFETS have similar properties, connecting the gate to the source with a small capacitor to imitate the electret biasing.

Incidentally, while doing this experimenting, I found a bug in the Waveforms 2015 code: if you sweep the frequencies downward in the network analyzer (which works), on output to a file the frequencies are misreported (as if they had been swept upward). I reported this on the Digilent Forum, and they claim it will be fixed in the next release. The time between the report and the acknowledgement was only a few hours, which is one of the fastest responses I’ve seen for a software bug report. (They didn’t say when the next release will be, but they’ve had several since I bought my Analog Discovery 2 four months ago, so they seem to be releasing bug fix versions rapidly.)

2015 July 9

Negative resistance in nFETs

Filed under: Circuits course — gasstationwithoutpumps @ 12:33
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I’ve been puzzling over the source of the negative dynamic resistance in the PSMN022-30PL nFETs that I reported on in Testing nFET with function generator, which looks a lot like what I saw with the NTD5867NL nFETs in  More mess in the FET modeling lab, but did not see with the AOI518 nFETs in Diode-connected nFET characteristics.

I replottted the I-vs-V curves for the diode-connected PSMN022-30PL as an R-vs-V curve, to get a better feel for the magnitude of the resistances.

The absolute resistances are still large in the range I'm examining—much larger than the on-resistance of 20mΩ–100mΩ shown on the data sheet.

The absolute resistances are still large in the range I’m examining—much larger than the on-resistance of 20mΩ–100mΩ shown on the data sheet.

Looking at the PSMN022-30PL data sheet in more detail, I can see that the nFET was not intended to be used at Vds=1.8V.  When the nFET is on, with the 20mΩ to 30mΩ on-resistance, the maximum current of 30A would limit Vds to about 0.9V, and the power limitation of 41W would limit Vds to about 1.1V.  We’re nowhere near the current or power limits, of course, but power nFETs are not usually kept in the range where they are just beginning to turn on.

I looked at the parasitic devices that come with a power nFET:

I did not get much help from friends on the EE faculty, who suggested that the parasitic BJT was latching up. But latchup is basically irreversible and occurs at large voltages—I’m barely turning the nFET on and I can trace the negative resistance region back and forth with no problem.

I have a conjecture now, but I don’t have enough information to really confirm it.  I think that the parasitic JFET is controlling the current in this region.  The JFET is in series with the MOSFET, and its resistance increases as Vds increases.  Normally Vds is kept small enough that the JFET resistance is not a problem, but I’m looking at a region where Vds is somewhat larger than normally used, so the JFET may be controlling the total resistance—the depletion regions around the p– body (that form the body diode) may be large enough to almost pinch off the drain connection to the channel.  As current flow through the JFET increases, Vds drops until the depletion regions separate making a clear path between the channel and the drain, and the JFET is no longer the main resistance—the other parasitic resistances dominate and Vds goes up with current again.

This explanation helps me understand why some power FETs exhibit the negative dynamic resistance and some don’t—the parasitic JFETs are very dependent on the geometry of the channel-to-drain connection.  Indeed, trench nFET designs decrease the effect of the parasitic JFET considerably.

I’m still a bit confused, though, as I have to get the voltage up to about 1.8V (and current to about 6mA) before the negative-resistance behavior starts.  Where is the state information stored that determines whether the resistance is 50Ω or 27kΩ when Vds is 1.5V? Could it be accumulated charges along the oxide that determine whether the channel (of the MOSFET) is on or not?

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