I gave the last of the lectures on class-D power amps today, starting by answering a question about how they could hook up a phone or iPOD to the power amp. Basically, the line output replaces the microphone and preamp circuit, before the high-pass filter that recenters the voltage, which is convenient, as they have mostly been building the preamp on a separate breadboard, with only two wires over to the class-D power stage. I also had the students figure out how to combine a left and right signal into a single monaural signal (as with most of the questions in the class, the answer is a voltage divider).
For most of the lecture I talked about how to decide whether the pull-up resistors for the open-collector comparators outputs needed to be bigger or smaller. I gave up on doing anything mathematical, and went for more cut-and-try approach (many, but not all, of the students already made mathematical estimates in the prelab, sometimes reasonably, sometimes off by moderate amounts).
The basic idea is simple: look at the output high voltage and the output low voltage. The output high voltage is whatever the other end of the resistor is connected to—for the pFET gate this is the same power rail as the pFET source is connected to, so it guaranteed to be high enough to turn the pFET off, while for the nFET gate this can be either ground or the positive power rail, which are guaranteed to turn the nFET on, as long as the power supply voltages are high enough. The output low voltage results from the voltage drop across the pull-up resistor, so is if that voltage is enough above the bottom power rail for the comparator output transistor to be saturated. The saturation current for the LM2903 they are using is guaranteed to be at least 6mA on the data sheet, but in practice is typically larger.
One thing I did not do was include a current-vs-voltage graph for the LM2903 comparator, though I had created one two years ago—I’ll have to put it in the book!
There are two regions of operation for the open-collector output of the LM2903. In the saturation region, the current goes up slowly with voltage (as about V^0.15, while in the “linear” region, it goes up as about V^1.5). The transition occurs when VOL is about 0.25 V, so we are almost always in the saturation region.
I probably should have presented this graph (I’d forgotten I had made it) and then justified using a saturation current of 10–16mA (maybe 12mA for the nFET driver where we want the low output to be well below the nFET threshold voltage and 16mA for the pFET driver, where we may not need to get anywhere near the lower power rail).
So the main constraint on the pull-up resistors is that they must be large enough to make the VOL voltages low enough to turn on the pFET, , and turn off the nFET, .
But making the resistors large slows down the upward transitions, making the pFET turn off slowly and the nFET turn on slowly, so we really want to make the resistors about as small as we can while reliably turning the pFET on or the nFET off. (This is an oversimplification, because the on-resistance of the FETs drops as we turn them on more firmly, so there is an incentive not to use the smallest possible values—but that tradeoff gets complicated without either measuring actual power consumption or doing extensive simulation.)
I then showed the students how to get the turn-on or turn-off time by looking at the gate voltage of the FET when the FET was switching a load (using the loudspeaker as a load, since they don’t have 8Ω 10W resistors). The time is from when the gate starts to change until the end of the Miller plateau, and I showed them the slowed down transition plots that I made for the book:
Here are the gate and drain voltages for an AOI518 nFET, slowed down by adding a series resistor to the gate signal and a large capacitor between the gate and drain. I slowed it down so that I could record on my low-speed BitScope USB oscilloscope—students can see high-speed traces on the digital oscilloscopes in the lab. The Miller plateaus are the almost flat spots on the gate voltage that arise from the negative feedback of the drain-voltage current back through the gate-drain capacitance.
I should probably take some of the 9–10 hours I’ll be spending in the lab tomorrow to try to make plots without the slowdown, using the high-speed digital oscilloscopes in the classroom. The oscilloscopes can save screen images onto flash drives with a single button push, but I’ve not yet figured out how to get data off of them in a usable format—I guess I’ll need to look in the manual (there is a copy cabled down in the lab).
I also mentioned the problem of overshoot when using only one FET (rather than the cMOS arrangement) to switch an inductive load, and showed how to use a flyback diode to provide a return path for the current that continues to flow from the inductor. With the cMOS arrangement, the built-in body diodes of the FETs provide good flyback diodes, with each FET’s body diode protecting against the overshoot when the other FET turns off. I should probably have some plots of that overshoot also for the book.
One thing I did not get enough time for in class is talking much about the LC filter design for removing the high-frequency PWM signal and delivering just the audio signal to the loudspeaker. I showed them the basic idea, and pointed them to the gnuplot script I’d written for them (where they need to plug in their own loudspeaker model), but I did not get a chance to demo it. I think that only the top third of the class got enough to be able to choose the capacitor (I only have one size of inductor available—I should probably buy a few other sizes). I covered the LC filter better last year (see post on that lecture), but I did a little better with real power this year.
Overall, it was not a great lecture—too much material and too sloppily done, so that I’m not sure that any of it got through clearly. Being so short on sleep for the past couple of weeks has really been killing my performance. Still, I think it was a little better than last Monday’s lecture, which was probably the worst of the quarter.