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2018 October 28

Redrawing figure in SVG

Filed under: Circuits course — gasstationwithoutpumps @ 20:18
Tags: , , , , , ,

There is a figure in my book of the cross-section of a power nFET.  Originally, I used a figure from wikimedia: https://en.wikipedia.org/wiki/Power_MOSFET#/media/File:Vdmos_cross_section_en.svg, but I wanted a color version, so I colorized it myself in Inkscape.  Unfortunately, the original SVG was poorly done—it looked like an inkscape conversion of a raster image to paths, which did not result in paths enclosing fillable areas with clean strokes around them, but separate paths filled with black for each stroke.  This made colorizing the image quite difficult.  I did (eventually) manage to make a colorized version, but I’ve never been happy with it.  The file is huge for an SVG file (over 81kB) and difficult to edit.  I’ve been wanting to do it right for some time, and I finally got around to it today.

What I did was to print out the version I’ve been using as a full-page image, then used a ruler to figure out how big each part was.  I then entered SVG code by hand to remake the image. I included comments to describe what each part did and used styles for the different materials, so editing is now easy.  I also made sure that the image is now symmetric and that all the rounded corners have smooth joins to the straight lines (the “q” command in the path “d” attribute makes that fairly easy. The new svg file is only 3425 bytes, even with the comments, and the pdf created from it is only 8kB, instead of 28kB.  Those size changes are not very important (the PDF for the book, after all, is now 25MB, up from 23.7MB last spring), but the image looks better now also.

WordPress.com does not let me upload svg files, but you can see the PDF produced from it by inkscape at https://gasstationwithoutpumps.files.wordpress.com/2018/10/nfet-cross-section.pdf

WordPress.com only lets me upload raster images for display, so I used inkscape to convert the hand-written SVG file to PNG just for this blog. The black line on the right edge seems to have been chopped off in the conversion, though the PDF conversion gets it right.

Here is the PNG generated by inkscape from the SVG file.

I tried uploading the SVG file to Wikimedia Commons, so it could be used on the Wikipedia Power MOSFET page, in place of the black-and-white image, but the uploaded file got rendered as a badly wrong black-and-white PNG file (with all colors converted to black), which is totally useless. I don’t have time to figure out how to tell it to do the conversion correctly, so I just asked them to delete the image again.

Here is the source code for the svg file, which I’m releasing with CC-BY-SA 4.0 (the original on WIkipedia that it was based on was released by Cyril Buttay as CC-BY-SA 3.0).











.label {font: italic 8px sans-serif;}
.super {font: italic 6px sans-serif; }
.arrow {stroke:black; fill:none; stroke-width:1; marker-end:url(#head) }
.wire {stroke:black; fill:none; stroke-width:1;}
.metal {stroke:black; fill:blue; stroke-width:1;}
.Nplus {stroke:black; fill:deeppink; stroke-width:1;}
.Nminus {stroke:black; fill:lightpink; stroke-width:1;}
.Pplus {stroke:black; fill:lightcyan; stroke-width:1;}
.poly {stroke:black; fill:tomato; stroke-width:1;}
.channel{stroke:none; fill:springgreen; stroke-width:1;}


<!-- Drawing the nFET cross-section in layers -->

<!-- the Nminus layer that is the bulk of the FET -->

N–

<!-- the drain including metal layer -->


Drain



<!-- the Nplus layer for the drain -->

N+

<!-- left source -->



Source


P+

N+



<!-- right source -->

P+

N+



<!-- gate -->



Gate



<!-- channel -->



Channel




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2018 February 25

Weekend off!

Filed under: Uncategorized — gasstationwithoutpumps @ 15:43
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I had only 2 hours of grading to do this weekend (but next weekend will make up for that, with more than 30 hours of grading), so I got a chance to do some other things for a change:

  • Buy groceries at Trader Joe’s.  (“Groceries” is misleading here, as I generally view Trader Joe’s as a beverage store—I bought soy milk, mineral water, hard cider, beer, port, and whiskey, plus cereal, chocolate, and prunes.  I don’t drink whiskey or mineral water and my wife doesn’t drink port or soy milk, but the cider and beer are for both of us.)
  • Do a protein structure prediction for a microbiology colleague.  I no longer use my own tools for protein-structure prediction, as they have succumbed to the changes in C++ and operating systems, so that they can no longer be compiled or run.  I’ve also not maintained the template library for several years.  Because the only predictions I get asked to make these days are ones for which there are good templates, I just use HHpred and Modeller on-line.  For that sort of prediction, they are quick and do an adequate job.  The goal of this prediction was to get a good guess of binding-site residues for a chemosensor, to guide site-directed mutagenesis.  Unfortunately, the available structures did not have ligands bound, and for most of them no one knows what the real ligand is anyway, so I had to make guesses based on the structure without solid evidence for how ligands bind to them.
  • Check whether the nFET and pFET we’ll be using next quarter have small enough gate capacitances to be driven directly from a comparator, or whether we’ll still need to use 74AC04 inverters as digital amplifiers.  We could probably just barely get away with using the comparators, but the chips end up running rather warm, so I’m still going to recommend using the digital amplifier.   One inverter for both the nFET and pFET gate seems to be fine, though—the rise and fall time is short enough that we don’t need to use a separate inverter for each gate.
  • Review courses for the Committee on Courses of Instruction meeting tomorrow—I only had 13 courses to review this time, and I’d already looked at half of them.

I still have this evening—maybe I’ll repot the free live Christmas tree my wife picked up yesterday.  We gave our old one away in January, because it was getting pot bound and we did not want to transfer it to a larger pot—the current one was as heavy as we could haul up the steps.  The new one is tiny, but should last us several years before it gets to be too big.  Today might also be a good day to put the Christmas ornaments back in the attic—we’ll probably have to rebox some of them, as Marcus (our kitten) has shredded some of the boxes.)

2018 January 17

Long weekend, little done

Filed under: Circuits course — gasstationwithoutpumps @ 10:01
Tags: , ,

Last weekend was a long weekend (Martin Luther King Day on Monday), and I briefly had fantasies of getting a lot of stuff done.  The trouble is I never settled on exactly what it was I would get done, so I ended up doing very little.  I read science fiction, I slept a lot, I tinkered with my book a little bit, I got the live Christmas tree out of the house, and I adjusted the brakes on my bike. but that’s about it.

The main addition to the book wasn’t even a very important one—this picture:

Some of the most common packages for FETs.

We used to use TO-220 and TO-251 packages for the class, since that is how power FETS are most commonly packaged, but the power FETs are getting expensive (the cheapest ones keep getting discontinued—maybe they were cheap because they were end-of-life, or maybe they were discontinued because there wasn’t enough profit at the low price point).  We had problems last year with TO-251 packages not staying in the breadboards—the springs seemed to pop the leads out rather than grabbing them.

This year we’ll be using the SOT-23 transistors, which are much cheaper, and soldering them to a breakout board.  I’m a little worried about how many of the students will have trouble with hand-soldering the small parts.  They’ll have had a little more practice soldering by then, so I’m hopeful that it will go ok.

The other changes to the book were mostly typo fixes for problems found by my students.  The students have been very good this year at reporting problems to me, and there were a lot more typos than I expected (averaging about 1 every 3 pages).  So far they’ve not pointed out any substantive errors, though there was one omission that I’ve fixed—it seems that some students have not heard of raster image formats, and thought I was trying to say “faster image formats”, so I’ve added a couple of paragraphs about image formats.  The changes that I’m making this quarter will be in the next release, which will probably be in March, during spring break.

2018 January 3

SOT-23 FETs for half H-bridge

Filed under: Circuits course — gasstationwithoutpumps @ 20:53
Tags: , , , , ,

In Breakout board for SOT-23 FETs, I gave the schematic and layout pictures for a half H-bridge breakout board using SOT-23 surface-mount FETs.  The boards arrived today, 12 days after I ordered them. The boards cost $4.86 plus $23.79 shipping, but I had them panelize the design, and they sent me 13 copies instead of 10, so I ended up with 546 boards (instead of 420), making a cost of 5.24¢ each.

One of the panelized board. The panels are just separated with V cuts, so the corner rounding is not very good, but there is some, and I did not end up with sharp corners after cutting off a row of boards with tin snips.

With the transistors, capacitor, and headers, each half H-bridge will cost under 40¢ in 100s—much less than the approximately $1.37/half H-bridge that separate TO-220 FETs cost.

Today I tried soldering on a  PMV20XNER nFET (14.9¢ in 100s) and SSM3J332R pFET (12.4¢ in 100s), a 5-long right-angle header, and a 10µF ceramic capacitor. I wanted to do this with pretty much the same tools the students would have, so I did not use a board holder nor cross-lock tweezers (both of which would have made the job slightly easier).  My technique was simple:

  • Put the board face up on the bench.
  • Place one FET using sharp-pointed tweezers.
  • Tape the FET and the drain side down with a tiny piece of blue painters’ tape.
  • Solder the source and gate.
  • Remove the tape.
  • Solder the drain.
  • Repeat for the other FET.
  • Put the headers through the holes (from the component side).
  • Flip the board over and solder the header.
  • Put the header pins into a breadboard at the edge of the board.
  • Insert the capacitor from the component side.
  • Prop the breadboard up so the solder side of the board is exposed.
  • Solder the capacitor in place and trim its leads.

Soldering the first board went well.  The second one was a little harder (I had a bit of hand tremor), but still only took a few minutes.  Having made the lands huge (big enough for wave soldering) made alignment fairly simple—I did not have to be exact.

I tried one FET without the trick of taping the FET in place—that did not work at all, as the FET moved completely off the pad when I tried to solder.  I had to remove solder from the board with a solder sucker and redo the FET using tape.

Here are the front and back of the boards before and after populating, along with the pointed tweezers I used for placing the FETs.

Here is a close-up of one of the two boards I soldered (the one with the worst alignment—see the pFET at the top left).

I spent the rest of the afternoon checking that the boards were OK.  I used essentially the same setup as I used for Ron vs Vgs for pFETs and nFETS, with a 24Ω load and a 10V ramp that gradually turned the transistor off.  Because the test was the same, I plotted the results together with the old results:

The PMV20XNER transistor has a much lower threshold than the other nFETS I’ve looked at, but a comparable Ron to the other power nFETs.

The SSM3J332R pFET also has a low threshold voltage and the on resistance is in the same range as others we have used in the past.

It looks to me like the half-H-bridge will be a perfectly reasonable way for the students to get FETs for the class-D amplifier.  The current will be somewhat limited by the power dissipation of the pFET, but with an 8Ω speaker and 0.1Ω pFET, the power to the loudspeaker should be 80 times the power lost in the pFET, so the 10W limit on the loudspeaker should be reached well before the half H-bridge overheats.

Update: the EAGLE and Gerber files for this board are available at https://users.soe.ucsc.edu/~karplus/bme51/pc-boards/

2017 December 22

Breakout board for SOT-23 FETs

Filed under: Circuits course — gasstationwithoutpumps @ 23:25
Tags: , , , , , ,

After a discussion in the comments of Ron vs Vgs for pFETs and nFETS with Michael Johnson, I decided to design my own breakout boards for SOT-23 surface-mount FETs, with the possible use of them in the class-D amplifier lab in place of the through-hole TO-220 FETs we’ve been using.

I picked a couple of 30V FETs (one nFET, one pFET) whose data sheets indicated that they would have adequately low on-resistance with a gate voltage of only 2.5V (–2.5V for the pFET), so that the FETs could be controlled by a 3.3V logic signal with no problems.  I ended up picking PMV20XNER for nFET (14.9¢ in 100s) and SSM3J332R for pFET (12.4¢ in 100s).

Although the drain-to-source voltage is allowed to go to 30V, the gate-to-source voltage is more limited (±12V for both the nFET and the pFET).  That should be adequate for anything we do in the course, as our maximum power supply is ±5V, so we shouldn’t see any voltage differences bigger than 10V.  (I could have saved a few cents by using 20V FETs instead of 30V ones, maybe.)

Because the students use the FETs in an H-bridge, I decided to make my breakout board be a half H-bridge, with an nFET, a pFET, a bypass capacitor, and 5 right-angle header pins:

The schematic is quite simple. (The diodes are the body diodes of the FETs.)

The layout took me a while, because I wanted to make as much heat sinking as I could get on a small, cheap board.  The standard footprint for a ST-23 allows a thermal resistance of about 120 K/W. I did not push too hard though, because even with ideal layout, the SOT-23 packages still have terrible thermal conductivity (about 90 K/W)—essentially all the heat is being conducted through the thin drain pin.  (The SSM3J332R reports even worse numbers: 300 K/W with minimum footprint and 120 K/W with a square inch of copper.)

Solder side of the board. Visualization provided by https://gerber-viewer.easyeda.com/

Component side of the board. Visualization provided by https://gerber-viewer.easyeda.com/

My board is not nearly a square inch of copper—the entire board is only 15mm × 12.5mm, and only half of that is used for heatsinking the drains. I used the back of the board for radiating heat and provided thermal vias around the drain pads to connect the front and back. The footprint for the pads is one provided by the manufacturers for wave soldering—I thought it would be easier for had soldering than the much smaller pads used for reflow soldering.

The gate connections are on the outside, the source connections just inboard of them, and the shared drain in the middle.  The board is basically symmetric with respect to nFET and pFET, but I labeled the two sides so that there would be less variation in how students soldered them up.

The bypass capacitor is close to the FETs (much closer than the students ever got on a bread board), so we should see less noise injection back into the power rails than we’ve seen in the past. The resistance of the source and drain traces adds another 5mΩ of resistance to the H-bridge, which is not too bad—the beardboard probably adds more like 50mΩ.

If I understood their website correctly, I should be able to get 10 copies of the tiny board panelized in a 6×7 array (so 420 boards after I cut them apart) for only $4.90 from Smart-Prototyping.com.  Of course, I’m in a hurry, so I ended up paying an extra $23.79 for shipping with DHL, so the order costs $28.69, or <7¢ a board.  I also ordered 10 40-pin right-angle male headers (enough for 80 boards) for $4.11 from AliExpress, raising the price to 12¢ a board.

With the transistors, each half H-bridge will cost under 40¢ in 100s—much less than the approximately $1.37/half H-bridge that the separate TO-220 FETs cost.

The difference in cost is not important for the course ($2 a student), so my main consideration is whether the students will learn more by doing some surface mount soldering with a fixed cMOS half-H-bridge design or by continuing to wire up separate transistors on the bread board (making the usual student errors of getting the pinout wrong or general miswiring).  There is still plenty of room for error on the half H-bridge: swapping transistors, getting 2 nFET or 2 pFET instead of one of each, putting the whole board in backwards to short the power supply through the body diodes, …. .

The SOT-23s can’t dissipate quite as much heat as the TO-220s, but we’ll probably not have much heat to dissipate in reasonable designs.  With a 5V supply, 8Ω load, and 73mΩ on-resistance, the power dissipation in the pFET should be only about 28mW and the nFET even less—way less than the 500mW or so that I expect the boards to be able to handle.  Shoot-through current is mainly what the students will need to worry about, as that can get quite high with the low on-resistances of both the nFET and the pFET.

I’ve ordered the boards and parts to test out using the SOT-23 FETs and half-H-bridge boards.  If they work out well, I’ll probably rewrite the class-D lab to have students do a little surface-mount soldering (SOT-23s are about the simplest intro).

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