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2017 May 16

New problem in class-D lab

Filed under: Circuits course — gasstationwithoutpumps @ 22:37
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Today was the last day for the class-D power amplifier lab, and the students had a problem that we’d never encountered before—the breadboards kept squirting the nFETs out of the breadboard (sometimes the landed several inches away).

We were using the same nFETs as last year,NTD4858N, which comes in a TO-251-3 Stub Leads (which they call IPak) package.  The problem is that this year’s breadboards have their contact springs deeper than in previous years, so the stub leads barely reach them.  I don’t know whether the breadboards were ordered from the supplier I had found (http://www.meerkatsystems.net/html/10000023.html) or whether they substituted one from one of their favorite suppliers.  It would be good to know, as this year’s breadboards seem to be inferior to previous year’s.

Next year, I think I’ll specify the nFET to be PSMN022-30PL,127, which comes in a TO-220 package and sits more firmly in the breadboard.

Tomorrow I’m giving a quiz in class—something I try to avoid doing, but so many students have not been showing up for class nor turning in the required pre-lab homework that I was compelled to assess them some other way.  My guess is that the grade distribution will be similar to the distribution for the sum of the homework so far (out of 50 possible points):

 1.0  1
 1.5  2
 2.5  1
 3.0  1
 3.5  3
 4.5  1
 5.0  1
 5.5  1
 6.0  1
 7.0  3
 7.5  2
 8.5  5
 9.0  1
 9.5  4
10.0  4
11.0  1
11.5  2
12.0  3
12.5  4
13.0  1
14.0  1
14.5  1
15.0  1
16.0  3
16.5  2
17.0  2
19.0  2
19.5  1
20.0  1
20.5  1
21.5  2
24.0  1
25.5  1
26.0  1
27.0  1
28.0  1
28.5  1
30.5  1
31.5  1
36.5  1

I further conjecture that there will be a very high correlation of scores (so I won’t really learn all that much about the students). But I’m prepared to be surprised—I made the quiz deliberately fairly easy, so it is possible that students who have struggled with the design problems of the homework may be able to do the quiz.

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2016 December 27

FET I-vs-V with Analog Discovery 2 again

 

In FET I-vs-V with Analog Discovery 2, I plotted Id vs. Vgs curves for an nFET:

The Ids-vs-Vgs curves do not superimpose as nicely as curves I’ve measured with PteroDAQ. I don’t yet understand why not.

Yesterday, I played with sweeping the power supply (Power waveform generator).  In this post, I used that capability to plot Id vs Vds curves for different gate voltages (Vgs) of a different nFET (since the AOI518 is an obsolete part).  The setup is the same as for the previous test—the function generator is connected to the gate, the power supply to the drain load resistor in series with the nFET whose source is connected to ground, and the two oscilloscope channels monitor the voltage across the load resistor and across the nFET.  The difference is that I use the power-waveform option to put a 1Hz triangle wave on the power supply, but put just a DC offset (AC amplitude 0V) on the function generator output, so that the gate voltage is constant as the drain voltage is adjusted.

The saturation regions are well plotted up to Vgs=2.7V. I averaged 10 or 20 scans for each of these curves, to reduce quantization noise for small voltages or small currents.

The saturation regions are well plotted up to Vgs=2.7V. I averaged 10 or 20 scans for each of these curves, to reduce quantization noise for small voltages or small currents.

I got quite different results when I removed and replaced the nFET from the breadboard—the breadboard contacts seem to have a variation of about ±0.05Ω in resistance, which is much larger than the on-resistance of the nFET when fully on. I took measurements with a wire between the source and drain to estimate the wiring resistance, but wiggling the wire produced very different results.

In the next graph, I tried subtracting off the wiring resistance to get the on-resistance, but I’m really quite dubious about the measurements smaller than 0.5Ω, because of the unrepeatability of the bread board contact resistance.

The numbers here look good (close to the spec sheet), but repeating the measurements could result in ±0.1Ω, which makes the Ron measurements for fully on transistors rather useless.

The numbers here look good (close to the spec sheet), but repeating the measurements could result in ±0.1Ω, which makes the Ron measurements for fully on transistors rather useless.

By using a smaller power resistor, I could probably get saturation currents for slightly higher gate voltages, up to the current limit of the power supplies in the Analog Discovery 2, but better on-resistance measurements would require a better jig for making low-resistance contacts to the FET.

By using a much larger resistor, I could measure low currents more accurately, which would give me a better idea of the leakage currents—I don’t really believe the measurements for Vgs=2.1V, because the current appears to decrease with increasing Vds, which is probably an artifact of measuring a small difference in voltage with a large common-mode signal.

I tried using larger resistors to measure the saturation currents, but the results varied a lot depending on what size load resistor is used. I believe that the difference is due to temperature changes from self-heating. If I sweep out to larger Vds voltages (using a smaller load resistor, hence smaller IR drop across it), but about the same saturation current, I’m dissipating more power in the transistor, so making it warmer. This appears to increase the saturation current. Reducing the range of the voltage with the same load resistor drops the curve down, just as increasing the load resistor does. I suspect that proper measurement requires a jig that holds the transistor at a nearly constant temperature, as well has having very low contact resistance.

The saturation current seems to vary by about ±10% as I change load resistors. The effect is most likely thermal—note that using a smaller voltage sweep for Vgs=2.3V and Rload=51Ω resulted in almost the same curve as Rload=270Ω, because the power dissipated was about the same.

The saturation current seems to vary by about ±10% as I change load resistors. The effect is most likely thermal—note that using a smaller voltage sweep for Vgs=2.3V and Rload=51Ω resulted in almost the same curve as Rload=270Ω, because the power dissipated was about the same.

Note that the thermal explanation also works for explaining why the superposition does not work well for the Id vs Vgs plots—at lower load resistances, more power is dissipated in the transistor, and it gets warmer, shifting the current curve upward.

2016 December 12

FET I-vs-V with Analog Discovery 2

Filed under: Data acquisition — gasstationwithoutpumps @ 17:41
Tags: , , , ,

Yesterday, in FET Miller plateau with Analog Discovery 2, I started posting about the Analog Discovery 2 USB oscilloscope, an oscilloscope with two differential input channels, 2 arbitrary-waveform function generators, a dual regulated power supply, and a logic analyzer.

I want to modify something I said yesterday:

If I look at the square wave with nothing but the scope attached, then I see a voltage of about 4.005V.  With a 100Ω load, I see 3.44V, which gives an output impedance of 16.4Ω.

I think that what I was seeing should not really be characterized as an output impedance, but as a current limitation.  The AD8067 op-amp that is the output device for the waveform generator is specified to have a 30mA current limitation (for -60dB spurious-free dynamic range) and 105mA short-circuit current, and 3.44V/100Ω is 34.4mA.  I can test this assumption by seeing what happens with a triangle-wave signal:

The triangle wave with a 100Ω load is clipped at approximately ±3.48V, corresponding to a current limitation of ±34.8mA.

The triangle wave with a 100Ω load is clipped at approximately ±3.48V, corresponding to a current limitation of ±34.8mA.

With 100Ω, I get ±3.48V, for ±34.8mA.  With 33Ω, I get ±1.475V, for ±44.7mA.  With 18Ω, I get +1.014V, -0.8458V, for +56.3mA, -47mA.  In each case, I am getting clear clipping, not scaling of the signal, so the best model is as a 0Ω output impedance, combined with current limitation, rather than as a non-zero output impedance.  The current limitation is not quite constant—I can get more current at lower voltages.

Something else you can see in the image above is that the time axis is not limited to starting at 0—I can move the trigger point around either graphically or by typing into boxes that hold the trigger level and time position for the line in the middle of the screen.

What I really wanted to show today was not the waveform generator current limit, but Ids-vs-Vgs plots for an nFET (the same old AOI518 nFET that I was playing with yesterday). I can use the differential inputs to measure the gate-to-source voltage on one channel and voltage across a drain resistor on the second channel.  It is easy to adjust the voltage range for a slow triangle wave driving the gate, and to look at an XY plot:

Voltage across 20Ω drain resistor to 5V for AOI518 nFET for a range of gate-to-source voltages. To get the large current, an external 5V wall-wart had to be connected.

Voltage across 20Ω drain resistor to 5V for AOI518 nFET for a range of gate-to-source voltages. To get the large current, an external 5V wall-wart had to be connected.

It would be nice if there were a way to scale the voltages across the load resistor to plot currents on the XY plot, instead of just voltages.  I can, of course, do this scaling with external programs, as I have with other measurement devices. I tried changing the resistors to get different current ranges, exporting the data in tab-delimited formats, and plotting superimposed I-vs-V plots. The results were not as good as I’ve gotten in the past using PteroDAQ:

The Ids-vs-Vgs curves do not superimpose as nicely as curves I’ve measured with PteroDAQ. I don’t yet understand why not.

I’m also not sure why there seems to be a 4µA leakage current.  At the top end, I’m not hitting the current limit of the voltage regulator, which is 700mA when powered by an external power supply, as I did here.

2016 December 11

FET Miller plateau with Analog Discovery 2

Filed under: Data acquisition — gasstationwithoutpumps @ 21:49
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I recently bought myself a birthday present: an Analog Discovery 2 USB oscilloscope. The device normally costs $279, but  I qualify for the academic discount, which brought the price down to $179—a very good deal.  This oscilloscope is better in every way than the Bitscope BS10 that I bought about 4 years ago: functions, resolution, bandwidth, software, … . The Analog Discovery 2 is also cheaper (at least with the academic discount).

I’ve been playing with it a little bit, and I decided to try to reproduce a few of the plots that I have done before.  This post is about creating the plot of the Miller plateau for an nFET (see, for example, More on nFET Miller plateau).  With the Bitscope, I had to filter the 5V power (which was just passed through the device, record many traces, process them with a program I wrote myself to remove the jitter in the triggering, average them, and plot with gnuplot).

With the Analog Discovery 2, I set the built-in power supply to 4V, set the function generator to a 1kHz square wave from 0V to 4V, and put the scope leads to measure Vgs and Vds for the following circuit:

The 100Ω gate resistor is to limit the current from the 1kHz square wave generator, so that the Miller plateau is stretched out in time.

This setup produced a very nice plot without any averaging—the Waveforms 2015 software that comes with the Analog Discovery 2 does the interpolation between samples to dejitter the waveform:

With a 100Ω gate resistance, the plateau is about 146ns long (easily measured with a pair of cursors not shown in this image).

With a 100Ω gate resistance, the plateau is about 146ns long (easily measured with a pair of cursors not shown in this image).

The average voltage is about 2.87V, so the current is (4V-2.87V)/100Ω=11.3mA, and the gate drain charge is 1.65nC, about half the 3.2nC on the data sheet (which was measured with different circuit parameters and is supposed to be a worst-case).  Note that this is a single trace, but multiple traces show almost no jitter, even though we are sampling at the full  100 Msample/second rate.  Averaging the traces would not make much difference in the signal.

If I replace the 100Ω gate resistor with a wire, I get a shorter Miller plateau:

With no gate resistor, the Miller plateau is only about 40.2ns long and averages 2.987V.

With no gate resistor, the Miller plateau is only about 40.2ns long and averages 2.987V.

If we assume 1.65nC in 40.2ns, we get a 41mA current, and (4V-2.987V)/41mA=24.7Ω for the output impedance of the function generator.  I may not have placed the cursors in exactly the same places on both curves, so this is a terrible way to estimate the output impedance of the function generator.

If I look at the square wave with nothing but the scope attached, then I see a voltage of about 4.005V.  With a 100Ω load, I see 3.44V, which gives an output impedance of 16.4Ω.

Of course, the square waves are not completely square, which may affect the Miller plateau measurement at high speed, but the edges are pretty sharp:

The falling edge takes about 50ns.

The falling edge takes about 50ns.

The rising edge takes about 50ns.

The rising edge takes about 50ns.

The edges are limited by the wiring, and I may be able to get better edges by using the BNC adapter board and 50Ω coax cable, rather than the wires provided, but I don’t happen to have any BNC coax cable handy.

2016 August 2

The real reason my nFET measurements were bad

Filed under: Circuits course — gasstationwithoutpumps @ 22:54
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In Why my nFET measurements were bad I observed a fixed minimum drain-to-source voltage for my nFET measurements, and claimed that this was the reason I couldn’t get consistent results for the on-resistance of  nFETs when measuring with small currents.

I worried about the result, though, because I really saw no reason for there to be a 20mV minimum Vds voltage. So I did what I should have done right away—set up a negative control. I used a piece of wire to connect the source and drain of the transistor being measured, and did the same Id vs Vds measurements.  This should produce a simple resistance that is very small (a few mΩ for the resistance of the breadboard). But I got the same 20mV minimum voltage as with the nFETs!

The problem turned out to be in my compensation for the offset of the unity-gain buffers—it corrected the value well, but could not correct the range—the smallest ADC output is 0, so if the offset correction makes a 0 ADC value correspond to a positive voltage, then that voltage is the lowest that can be reported.

Today I decided to correct the range as well, by making sure that the op-amp inputs stayed away from 0.  I added 470kΩ pullup to 3.3V to the voltage divider, so that with the input at 0v the output would be at about 83mV.  The Thévenin equivalent of the 470kΩ and 15kΩ resistors is a 14.54kΩ resistor to 102mV.

The new test fixture adds the 470kΩ pullups just to the Vds and Vdd measurements, as Vgs doesn't need to be measured near 0. Noise-reducing capacitors were added to all the op-amp outputs.

The new test fixture adds the 470kΩ pullups just to the Vds and Vdd measurements, as Vgs doesn’t need to be measured near 0.
Noise-reducing capacitors were added to all the op-amp outputs.

I recalibrated the test fixture to get the dividers’ ratios and offsets and measured the nFET again. I tried to let the transistor and load resistor warm up for a while before starting recording for each gate voltage, to avoid thermal drift (there still seems to be some drift for the Vgs=2.89V trace).

Now the curves look much more like the straight lines I expected (and I remembered to test the control: a drain-source short). With lower gate voltages, the nFET could not sink the full current.

Now the curves look much more like the straight lines I expected (and I remembered to test the control: a drain-source short).
With lower gate voltages, the nFET could not sink the full current.

I fit the equivalent resistance model by fitting V_{ds} = R I_{d}+ \epsilon, allowing for some residual offset in the Vds measurement. For computing the drain current, I not only used the corrected voltages for Vds and Vdd, but also subtracted off Vds/76.5kΩ, the approximate impedance of the voltage divider for Vds. The 80µA drain current for Vgs=0V is more than expected leakage for this nFET (1µA @20°C), and probably reflects the remaining imperfections of the test setup.

The on-transistors are on the left, never getting high voltage. The off-transistors are on the bottom, never getting high current. All the transistors curves stop at a parabola, determined by the power supply voltage and the load resistor.

The on-transistors are on the left, never getting high voltage. The off-transistors are on the bottom, never getting high current. All the transistors curves stop at a parabola, determined by the power supply voltage and the load resistor.

The maximum power that can be delivered to the nFET is a parabola determined by the 9V power supply and 10Ω load resistor—it passes through 0A at 0V and the power-supply voltage, with a maximum at half the power-supply voltage. I did have one run that traced out most of the parabola, including the peak at 4.5V, but I did not use that curve in this post, because it was collected before I added the noise-reducing capacitors at the inputs to the ADC.

The curve for Vgs=2.40V (weakly on) is the only one that shows much hysteresis due to thermal effects.  The changes in resistance and threshold voltage due to temperature are most important when you are very close to turning off the transistor, and the heating is most when the equivalent resistance of the channel matches the load resistor.

The resistances I’m measuring (105mΩ at best) are still much higher than I would expect based on the data sheet, which specs 9.3mΩ max with Vgs=4.5V (measured at 30A).

 

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