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2017 December 22

Breakout board for SOT-23 FETs

Filed under: Circuits course — gasstationwithoutpumps @ 23:25
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After a discussion in the comments of Ron vs Vgs for pFETs and nFETS with Michael Johnson, I decided to design my own breakout boards for SOT-23 surface-mount FETs, with the possible use of them in the class-D amplifier lab in place of the through-hole TO-220 FETs we’ve been using.

I picked a couple of 30V FETs (one nFET, one pFET) whose data sheets indicated that they would have adequately low on-resistance with a gate voltage of only 2.5V (–2.5V for the pFET), so that the FETs could be controlled by a 3.3V logic signal with no problems.  I ended up picking PMV20XNER for nFET (14.9¢ in 100s) and SSM3J332R for pFET (12.4¢ in 100s).

Although the drain-to-source voltage is allowed to go to 30V, the gate-to-source voltage is more limited (±12V for both the nFET and the pFET).  That should be adequate for anything we do in the course, as our maximum power supply is ±5V, so we shouldn’t see any voltage differences bigger than 10V.  (I could have saved a few cents by using 20V FETs instead of 30V ones, maybe.)

Because the students use the FETs in an H-bridge, I decided to make my breakout board be a half H-bridge, with an nFET, a pFET, a bypass capacitor, and 5 right-angle header pins:

The schematic is quite simple. (The diodes are the body diodes of the FETs.)

The layout took me a while, because I wanted to make as much heat sinking as I could get on a small, cheap board.  The standard footprint for a ST-23 allows a thermal resistance of about 120 K/W. I did not push too hard though, because even with ideal layout, the SOT-23 packages still have terrible thermal conductivity (about 90 K/W)—essentially all the heat is being conducted through the thin drain pin.  (The SSM3J332R reports even worse numbers: 300 K/W with minimum footprint and 120 K/W with a square inch of copper.)

Solder side of the board. Visualization provided by https://gerber-viewer.easyeda.com/

Component side of the board. Visualization provided by https://gerber-viewer.easyeda.com/

My board is not nearly a square inch of copper—the entire board is only 15mm × 12.5mm, and only half of that is used for heatsinking the drains. I used the back of the board for radiating heat and provided thermal vias around the drain pads to connect the front and back. The footprint for the pads is one provided by the manufacturers for wave soldering—I thought it would be easier for had soldering than the much smaller pads used for reflow soldering.

The gate connections are on the outside, the source connections just inboard of them, and the shared drain in the middle.  The board is basically symmetric with respect to nFET and pFET, but I labeled the two sides so that there would be less variation in how students soldered them up.

The bypass capacitor is close to the FETs (much closer than the students ever got on a bread board), so we should see less noise injection back into the power rails than we’ve seen in the past. The resistance of the source and drain traces adds another 5mΩ of resistance to the H-bridge, which is not too bad—the beardboard probably adds more like 50mΩ.

If I understood their website correctly, I should be able to get 10 copies of the tiny board panelized in a 6×7 array (so 420 boards after I cut them apart) for only $4.90 from Smart-Prototyping.com.  Of course, I’m in a hurry, so I ended up paying an extra $23.79 for shipping with DHL, so the order costs $28.69, or <7¢ a board.  I also ordered 10 40-pin right-angle male headers (enough for 80 boards) for $4.11 from AliExpress, raising the price to 12¢ a board.

With the transistors, each half H-bridge will cost under 40¢ in 100s—much less than the approximately $1.37/half H-bridge that the separate TO-220 FETs cost.

The difference in cost is not important for the course ($2 a student), so my main consideration is whether the students will learn more by doing some surface mount soldering with a fixed cMOS half-H-bridge design or by continuing to wire up separate transistors on the bread board (making the usual student errors of getting the pinout wrong or general miswiring).  There is still plenty of room for error on the half H-bridge: swapping transistors, getting 2 nFET or 2 pFET instead of one of each, putting the whole board in backwards to short the power supply through the body diodes, …. .

The SOT-23s can’t dissipate quite as much heat as the TO-220s, but we’ll probably not have much heat to dissipate in reasonable designs.  With a 5V supply, 8Ω load, and 73mΩ on-resistance, the power dissipation in the pFET should be only about 28mW and the nFET even less—way less than the 500mW or so that I expect the boards to be able to handle.  Shoot-through current is mainly what the students will need to worry about, as that can get quite high with the low on-resistances of both the nFET and the pFET.

I’ve ordered the boards and parts to test out using the SOT-23 FETs and half-H-bridge boards.  If they work out well, I’ll probably rewrite the class-D lab to have students do a little surface-mount soldering (SOT-23s are about the simplest intro).

2017 December 20

Ron vs Vgs for pFETs and nFETS

Filed under: Circuits course — gasstationwithoutpumps @ 22:16
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My son has joked that I don’t have an electronics hobby—I have a hobby of characterizing transistors.  There is an uncomfortable amount of truth in that assertion—I spend more time measuring things with my tools than building things.

Today I wanted to characterize all the nFETs and pFETs that I have, so that I could choose the right ones for the class-D amplifier lab in spring quarter—also to see whether the on resistances were as low at the data sheet claimed.

I used just the Analog Discovery 2, some 10W resistors (to make the 24Ω load), and a Schottky diode as a fly-back diode (because the power resistors have a fairly large inductance).  I chose the load so that the power supplies on the Analog Discovery 2 would not exceed their 2.1W limit. In the past I’ve used a wall wart with a higher current limit to do power FET tests, but I figured that the 400mA test current was enough for what I wanted to do today.

The setup for measuring the pFETs.

I swept the gate voltage with a 1-second ramp, turning the transistor on abruptly but off slowly.  I determined the gate voltage just from the timing, as I used the two oscilloscope channels to measure the drain-to-source voltage Vds and the drain current Id.

The results of measuring the pFETs. Only the low-threshold IPP45P03P4L11AKSA1 turns on at –3.3V. The funny knees in the curve around 10Ω are where the test jig switches from being roughly constant current (~400mA) to having a current dependent on Ron (Vds is no longer nearly 0).

To get the on resistance, I fit the data from –10V to –9V with a straight line and used that straight line at Vgs=–10V to get the value.

IPP45P03P4L11AKSA1 is no longer available, but NTD2955-1G and IRFU9024NPBF still are—it’s too bad that they aren’t really turned on at —3.3V.  Perhaps I should get myself some IRLIB9343PBF pFETS and test them—they supposedly have a very low threshold and reasonably low Ron. They cost a bit more, but they do have the longer leads that allow breadboarding.  I looked at the data sheet for the IRLIB9343PBF, and it does not look very promising—the resistance shoots up at about –5V.  The SPP15P10PLHXKSA1 looks more promising on the datasheet.

I have a lot more nFETs than pFETs, so I tested all of them also. The circuit is essentially the same as for the pFETs, just swapping the voltage sources and turning the fly-back diode around. I also changed the direction of the ramp, so that I was still turning on the FET abruptly and off slowly.

The nFETs clustered more than the pFETs did, with three outliers.

One of the outliers, IPU50R950CEAKMA1, is a high-voltage nFET. It has both a high threshold and a high Ron, but it can handle much larger voltages than the others—it was intended for switching rectified mains voltages (about 350V), but I’ve not used it yet. The other two outlier nFETs (2N7000TA and TN2106N3-G) are not power FETs—I had to switch to a 48Ω load to measure them, to avoid putting too much current through them.

The AOI514 and AOI518 parts are obsolete. The NTD4858N-35G is still available, but it has very short leads, and we had problems last year with them popping out of the breadboards. The NTD5867 is now only available as a surface-mount part, but the PSMN022-30PL,127 is still available and has long leads that work in the breadboard.

2017 May 16

New problem in class-D lab

Filed under: Circuits course — gasstationwithoutpumps @ 22:37
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Today was the last day for the class-D power amplifier lab, and the students had a problem that we’d never encountered before—the breadboards kept squirting the nFETs out of the breadboard (sometimes the landed several inches away).

We were using the same nFETs as last year,NTD4858N, which comes in a TO-251-3 Stub Leads (which they call IPak) package.  The problem is that this year’s breadboards have their contact springs deeper than in previous years, so the stub leads barely reach them.  I don’t know whether the breadboards were ordered from the supplier I had found (http://www.meerkatsystems.net/html/10000023.html) or whether they substituted one from one of their favorite suppliers.  It would be good to know, as this year’s breadboards seem to be inferior to previous year’s.

Next year, I think I’ll specify the nFET to be PSMN022-30PL,127, which comes in a TO-220 package and sits more firmly in the breadboard.

Tomorrow I’m giving a quiz in class—something I try to avoid doing, but so many students have not been showing up for class nor turning in the required pre-lab homework that I was compelled to assess them some other way.  My guess is that the grade distribution will be similar to the distribution for the sum of the homework so far (out of 50 possible points):

 1.0  1
 1.5  2
 2.5  1
 3.0  1
 3.5  3
 4.5  1
 5.0  1
 5.5  1
 6.0  1
 7.0  3
 7.5  2
 8.5  5
 9.0  1
 9.5  4
10.0  4
11.0  1
11.5  2
12.0  3
12.5  4
13.0  1
14.0  1
14.5  1
15.0  1
16.0  3
16.5  2
17.0  2
19.0  2
19.5  1
20.0  1
20.5  1
21.5  2
24.0  1
25.5  1
26.0  1
27.0  1
28.0  1
28.5  1
30.5  1
31.5  1
36.5  1

I further conjecture that there will be a very high correlation of scores (so I won’t really learn all that much about the students). But I’m prepared to be surprised—I made the quiz deliberately fairly easy, so it is possible that students who have struggled with the design problems of the homework may be able to do the quiz.

2016 December 27

FET I-vs-V with Analog Discovery 2 again

 

In FET I-vs-V with Analog Discovery 2, I plotted Id vs. Vgs curves for an nFET:

The Ids-vs-Vgs curves do not superimpose as nicely as curves I’ve measured with PteroDAQ. I don’t yet understand why not.

Yesterday, I played with sweeping the power supply (Power waveform generator).  In this post, I used that capability to plot Id vs Vds curves for different gate voltages (Vgs) of a different nFET (since the AOI518 is an obsolete part).  The setup is the same as for the previous test—the function generator is connected to the gate, the power supply to the drain load resistor in series with the nFET whose source is connected to ground, and the two oscilloscope channels monitor the voltage across the load resistor and across the nFET.  The difference is that I use the power-waveform option to put a 1Hz triangle wave on the power supply, but put just a DC offset (AC amplitude 0V) on the function generator output, so that the gate voltage is constant as the drain voltage is adjusted.

The saturation regions are well plotted up to Vgs=2.7V. I averaged 10 or 20 scans for each of these curves, to reduce quantization noise for small voltages or small currents.

The saturation regions are well plotted up to Vgs=2.7V. I averaged 10 or 20 scans for each of these curves, to reduce quantization noise for small voltages or small currents.

I got quite different results when I removed and replaced the nFET from the breadboard—the breadboard contacts seem to have a variation of about ±0.05Ω in resistance, which is much larger than the on-resistance of the nFET when fully on. I took measurements with a wire between the source and drain to estimate the wiring resistance, but wiggling the wire produced very different results.

In the next graph, I tried subtracting off the wiring resistance to get the on-resistance, but I’m really quite dubious about the measurements smaller than 0.5Ω, because of the unrepeatability of the bread board contact resistance.

The numbers here look good (close to the spec sheet), but repeating the measurements could result in ±0.1Ω, which makes the Ron measurements for fully on transistors rather useless.

The numbers here look good (close to the spec sheet), but repeating the measurements could result in ±0.1Ω, which makes the Ron measurements for fully on transistors rather useless.

By using a smaller power resistor, I could probably get saturation currents for slightly higher gate voltages, up to the current limit of the power supplies in the Analog Discovery 2, but better on-resistance measurements would require a better jig for making low-resistance contacts to the FET.

By using a much larger resistor, I could measure low currents more accurately, which would give me a better idea of the leakage currents—I don’t really believe the measurements for Vgs=2.1V, because the current appears to decrease with increasing Vds, which is probably an artifact of measuring a small difference in voltage with a large common-mode signal.

I tried using larger resistors to measure the saturation currents, but the results varied a lot depending on what size load resistor is used. I believe that the difference is due to temperature changes from self-heating. If I sweep out to larger Vds voltages (using a smaller load resistor, hence smaller IR drop across it), but about the same saturation current, I’m dissipating more power in the transistor, so making it warmer. This appears to increase the saturation current. Reducing the range of the voltage with the same load resistor drops the curve down, just as increasing the load resistor does. I suspect that proper measurement requires a jig that holds the transistor at a nearly constant temperature, as well has having very low contact resistance.

The saturation current seems to vary by about ±10% as I change load resistors. The effect is most likely thermal—note that using a smaller voltage sweep for Vgs=2.3V and Rload=51Ω resulted in almost the same curve as Rload=270Ω, because the power dissipated was about the same.

The saturation current seems to vary by about ±10% as I change load resistors. The effect is most likely thermal—note that using a smaller voltage sweep for Vgs=2.3V and Rload=51Ω resulted in almost the same curve as Rload=270Ω, because the power dissipated was about the same.

Note that the thermal explanation also works for explaining why the superposition does not work well for the Id vs Vgs plots—at lower load resistances, more power is dissipated in the transistor, and it gets warmer, shifting the current curve upward.

2016 December 12

FET I-vs-V with Analog Discovery 2

Filed under: Data acquisition — gasstationwithoutpumps @ 17:41
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Yesterday, in FET Miller plateau with Analog Discovery 2, I started posting about the Analog Discovery 2 USB oscilloscope, an oscilloscope with two differential input channels, 2 arbitrary-waveform function generators, a dual regulated power supply, and a logic analyzer.

I want to modify something I said yesterday:

If I look at the square wave with nothing but the scope attached, then I see a voltage of about 4.005V.  With a 100Ω load, I see 3.44V, which gives an output impedance of 16.4Ω.

I think that what I was seeing should not really be characterized as an output impedance, but as a current limitation.  The AD8067 op-amp that is the output device for the waveform generator is specified to have a 30mA current limitation (for -60dB spurious-free dynamic range) and 105mA short-circuit current, and 3.44V/100Ω is 34.4mA.  I can test this assumption by seeing what happens with a triangle-wave signal:

The triangle wave with a 100Ω load is clipped at approximately ±3.48V, corresponding to a current limitation of ±34.8mA.

The triangle wave with a 100Ω load is clipped at approximately ±3.48V, corresponding to a current limitation of ±34.8mA.

With 100Ω, I get ±3.48V, for ±34.8mA.  With 33Ω, I get ±1.475V, for ±44.7mA.  With 18Ω, I get +1.014V, -0.8458V, for +56.3mA, -47mA.  In each case, I am getting clear clipping, not scaling of the signal, so the best model is as a 0Ω output impedance, combined with current limitation, rather than as a non-zero output impedance.  The current limitation is not quite constant—I can get more current at lower voltages.

Something else you can see in the image above is that the time axis is not limited to starting at 0—I can move the trigger point around either graphically or by typing into boxes that hold the trigger level and time position for the line in the middle of the screen.

What I really wanted to show today was not the waveform generator current limit, but Ids-vs-Vgs plots for an nFET (the same old AOI518 nFET that I was playing with yesterday). I can use the differential inputs to measure the gate-to-source voltage on one channel and voltage across a drain resistor on the second channel.  It is easy to adjust the voltage range for a slow triangle wave driving the gate, and to look at an XY plot:

Voltage across 20Ω drain resistor to 5V for AOI518 nFET for a range of gate-to-source voltages. To get the large current, an external 5V wall-wart had to be connected.

Voltage across 20Ω drain resistor to 5V for AOI518 nFET for a range of gate-to-source voltages. To get the large current, an external 5V wall-wart had to be connected.

It would be nice if there were a way to scale the voltages across the load resistor to plot currents on the XY plot, instead of just voltages.  I can, of course, do this scaling with external programs, as I have with other measurement devices. I tried changing the resistors to get different current ranges, exporting the data in tab-delimited formats, and plotting superimposed I-vs-V plots. The results were not as good as I’ve gotten in the past using PteroDAQ:

The Ids-vs-Vgs curves do not superimpose as nicely as curves I’ve measured with PteroDAQ. I don’t yet understand why not.

I’m also not sure why there seems to be a 4µA leakage current.  At the top end, I’m not hitting the current limit of the voltage regulator, which is 700mA when powered by an external power supply, as I did here.

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