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2014 May 24

Class-D amplifier lecture 2

Filed under: Circuits course — gasstationwithoutpumps @ 17:41
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Yesterday, in the last lecture before the long weekend (hence before they start wiring their Class-D power amplifiers), I covered three topics:

• open-collector outputs.  I had hoped to avoid that this year by switching to the TLC3702 comparators, but I couldn’t get the TLC3702 comparators to work with the FETs, so I went back to using the LM2903 comparators that the students got in their parts kits.  Because I had already cut the open-collector information from the lab handout, I had to cover it in lecture, and I’ll have to write an addendum to the handout today.
• LC filters for the loudspeaker.  This was a pretty rushed job.  I didn’t even have time to get them to derive the LC filter behavior with no load (the standard voltage divider formula $\frac{Z_{down}}{Z_{up}+Z_{down}}$ becomes $\frac{1/(j \omega C)}{j\omega L + 1/(j \omega C)}=\frac{1}{1-\omega^2 LC}$, which goes to infinity at $\omega=1/\sqrt{LC}$ and 0 at DC and infinite frequency.  Instead I pointed them to a gnuplot script that they needtomodify to see how much power the LC filter delivers to the loudspeaker at different frequencies, with different choices of capacitor (no choices for them on the inductor—it is a 220µH 0.252Ω AIUR-06-221 inductor).

LC filter and loudspeaker model used for sizing the capacitor in the gnuplot script. The students need to replace the loudspeaker model with the one that they created in an earlier lab. I think that next year I may use a much simpler loudspeaker model in the script, so that I can tell whether the students have replaced the model or not.

The output of the gnuplot script looks something like this:

Output of the gnuplot script. Note that too small a capacitor results in a spike near 61kHz and nowhere near enough suppression of the 50kHz–100kHz PWM frequency. Too large a capacitor results in a big boost in gain around 3.8kHz, which would a different sort of problem. Click

• Block diagram for the class-D amplifier.  I had originally planned to spend almost the entire lecture having the students develop the block diagram, but the addition of almost 45 minutes on open-collector outputs and review of the FET driver stage left me with little time for the block diagram. I did get some participation from the class in developing the diagram, but almost entirely from one student.  I felt bad about presenting, rather than getting them to participate in creating the block diagram, but they had to have a block diagram to do their more detailed design over the weekend.One important point I that I emphasized, based on common problems on the second quiz, is that a block diagram is not a simple pipeline, but can have merging and splitting.  The class-D amplifier has merging of voltage generators for DC bias with the signal path and merging of the triangle wave generator with the signal path.
One good thing came out of the block diagram discussion: in putting together the design they had the output of the preamp centered at 3v but the input of the comparators centered a 0v.  I could point out that putting range information on the signal lines allowed them to catch this error early (before even doing the schematic).  Most of the class was able to come up with the standard solution for changing the C bias: adding a high-pass RC filter.  I don’t know whether they can choose a corner frequency appropriately, but we’ll see that on Tuesday.

I didn’t get a chance to teach them about real power, either, which the LC script computes.  I’ll have to go over that next Wednesday, between the two halves of the lab.  There is a writeup of the concept in the lab handout, but my experience has been that students in this class don’t learn from written material.

I’ve also told the students that they need to get all their required “REDO” assignments turned in by Wednesday.  It seems that this year’s class does not have the time-management skills to handle open deadlines—they keep putting off redoing the assignments.  Given that they sometimes don’t fix the assignments sufficiently when they turn them in again, leaving the assignments to the last week is really dangerous.  Next year I’ll have to make one-week deadlines for redoing the assignments, though I can be generous about extending deadlines on request.

Overall, the lecture was way too rushed, because of the extra coverage needed for open collectors. Next year I’ll have to make sure to allow 3 lectures for the class-D power amp, which means not having it on the week with Memorial Day.  I’ll probably want to move Quiz 2 a little earlier also, so that it isn’t the week before the class-D power amp.

2014 May 22

Class-D lab revision didn’t work

In Long weekend, I discussed what I was planning to do about anticipated problems with the class-D amplifier lab, specifically

• Replace the AOI518 nFET with one that has a lower input capacitance, such as the PSMN022-30PL,127.  The gate charge at VGS of 4.5v is 4.4nC, about half that of the AOI518.
• Replace the open-collector comparator with one that has push-pull output, like the TLC3072, which can provide ±20mA current (more than the LM2903, even before we allow for the current through the pullup resistor).

I did a neat version of the schematics last night using the TLC3072 comparators and the AOI518 nFET. This year I remembered to include an adjustable gain stage in the preamp, so that I could more easily control the volume. Today in the lab, while the students were soldering up their instrumentation amps for the pressure sensor, I wired up the class-D amplifier, one stage at a time, confirming that each stage worked using the oscilloscope before moving on to the next. The build took me longer than I had expected—almost 2 hours.

Everything worked fine until I connected the drains of the two FETs together.  Initially it worked ok, but after about 20 seconds the shoot-through current increased, causing the current limitation of the bench power supply to kick in.  Then the voltage on the lower power rail moved up  close to ground, and the input voltage on the comparator was swinging below the negative rail.  I think that this damaged a couple of my TLC3072 chips—I’ve marked them, and I’ll have to test them before using them.

Replacing the AOI518 transistor with the smaller  PSMN022-30PL,127 did not help.

I finally borrowed an LM2093P chip from one of the students (I’d left mine at home, by mistake) and tried replacing the TLC3072 chip with the LM2093P. They have the same pinout, but the LM2093P is an open-collector output, so I had to add pullup resistors.  I guessed a couple of values, based on vague recollections of last year’s design, and the amplifier worked.

Initially I could only run the amplifier up to ±7v on the power supply, without the FETs getting too warm—there was still too much shoot-through current during transitions.  I switched to a lower resistance for the pullup on the pFET gate, to make the voltage swing less and the turn-off faster.  At that point the amplifier worked quite happily with a ±8v swing without the transistors getting warm.The circuit worked with either of the nFET transistors, so I’ll just have the students stick with the AOI518 in their parts kit.

I couldn’t crank up the volume on the speaker, though, because I got feedback squeal whenever the gain got too high.  Perhaps I should make a long speaker extension cable for students to do testing next week.  I seem to be out of speaker wire, though.

The class-D amplifier design will be a tough one for the students, and I’ll need to do a supplemental handout on open-collector outputs (I’d cut that material from the handout when I thought that we would be using the TLC3072 comparators).

Last week I thought that the students could start on the class-D amplifier in lab today, having finished the soldering for the pressure-sensor amp on Tuesday, but it took almost the whole lab time today for students to finish the soldering, even though everyone had working breadboards on Tuesday.  The lab ran over by almost 2 hours for one group, taking a total of 8 hours instead of 6 (last year the same lab took only 4 hours for the slowest group, probably because last year’s class came to lab more prepared).

The layout took longer than students expected, as did the soldering.  Everyone did (eventually) get working soldered instrumentation amps, though for a couple of groups I had to point out that their wiring did not match their schematic (they had called me over to help debugging).

In one case they had connected a resistor to the wrong point in their circuit.  I found the bug by tracing where their virtual ground was connected, and asking them to identify each component. Even after I showed them both resistors connected to their virtual ground, where only one was supposed to be, it took them a long time to realize what the discrepancy was. They had wired exactly what they had laid out, but the bug was in their layout, and they had not done a thorough enough job of checking against their schematic.

Another group had a working circuit but with too little gain. After checking a few of the DC voltage levels with them, I compared each of their resistors to the schematic.  In one place they had wired in a 1kΩ resistor where the schematic called for a 10kΩ resistor.  They unsoldered the incorrect resistor and soldered in the resistor from the design, which salvaged the circuit.

I also returned Wednesday’s quiz in lab today—pretty much like last year, the scores were much better on the second quiz than the first one, though still only half what I think the students should be able to do at this point of the quarter.  I’m once again assigning the students to redo the quiz as homework.  I need to decide soon whether to give them another quiz during the final exam time.

2014 May 19

Long weekend

In Problems rewriting the Class-D amplifier lab I discussed the problems I was having with rewriting the class-D amplifier lab, and came up with the following ideas:

• Try the same basic design as last year, and see if I can get a power supply voltage and pullup resistor settings that work.  I’ll have to do this in the lab on campus, because I don’t have a power supply at home that provides the same voltage ranges.
• Replace the AOI518 nFET with one that has a lower input capacitance, such as the PSMN022-30PL,127.  The gate charge at VGS of 4.5v is 4.4nC, about half that of the AOI518.
• Replace the open-collector comparator with one that has push-pull output, like the TLC3072, which can provide ±20mA current (more than the LM2903, even before we allow for the current through the pullup resistor).
• Add a driver chip that is intended for driving a pair of FET transistors, like the FAN7382, which can provide very fast rise and fall times even into 1000pF loads. But the driver chips are intended for two nFET transistors, and the charge pump for the high-side driver would be difficult to explain in this course and requires external components (diodes, resistors, and capacitors) that the students would have no idea how to choose.
• Use an H-bridge or half-H-bridge chip instead of having students design the power stage with FETs.  Most are designed for controlling motors, and don’t give timing specs that would tell me whether they could handle a high enough PWM frequency for audio output.

Yesterday I ordered some TLC3072 comparator chips and some PSMN022-30PL,127 nFETs, also some MCP6004 op-amp chips, since I seem to have run out, and they are quite cheap.  (I probably need more instrumentation amp chips also, but they are more expensive so I’ll probably wait until I really need them). I hope that I can get the TLC3072 comparator chips before lab on Thursday, so that I can test out the circuit before the students need to build it.  Otherwise I’ll have to cycle into work over the weekend to test the lab. Digi-key shipped it this evening by first-class mail, which probably means I won’t get it until Friday—when they’ve shipped early Monday morning, I ‘ve gotten things by Thursday.

This weekend had me spending a lot of time on the circuits course—I estimate that I spent about 35 hours on the course from Friday night until Monday morning. In addition to figuring out how to rescue and simplify the class-D amplifier lab, I also had to rewrite all the tutorial material for the lab handout, create a quiz for Wednesday’s class, and grade their optical pulse monitor lab reports.

The grading is still a bit painful, as some of the students write nearly incomprehensible English and some are still making trivial mistakes on the schematics (like leaving out component values and shorting out components).  One error on this round was particularly worth commenting on to the class: consistently using mΩ when MΩ was meant.  What is a factor of a billion between friends?  About half the class still can’t explain sensitivity and gain computations, even when they get the right answer.  In some cases, they probably had not come up with the answer themselves, as they made mistakes that magically got cancelled and disappeared when they reported their final results. They keep such awful lab notebooks though, that it is quite possible that they had done the correct computation at one point, but could not reconstruct their work when they went to write it up a few hours later, so I won’t accuse anyone of cheating.

Today I collected prelab homework at the end of class.  The assignment of prelab homework to be turned in did get students to read the assignment and make a stab at doing the design work, and (for the first time) I got questions about the design on Monday rather than halfway through lab on Tuesday.  Most of the designs were incomplete and had serious errors, but at least an attempt had been made to understand the problem, and I was able to clear up several misunderstandings in class:

• Several students tried to put the op amps before the instrumentation amp.  I obviously had not made it clear what an instrumentation amp was for.
• Many of the students had not gotten the idea that an instrumentation amp is a single symbol in a schematic not a conglomeration of op amps and resistors.  This was probably my fault for trying to explain how an instrumentation amp works, rather than how to use one.  It doesn’t help that the INA126P data sheet shows only the innards, and not the external view of the amplifier. I think that next year I may skip explaining how an instrumentation amp works internally, though I think it is kind of cool.

Instrumentation amplifier symbol. I prefer putting Vref on the bottom, rather than the top of the amplifier, but either way works.

• I spent a fair amount of time trying to help the students understand the notion of output voltages being referenced to a specific other voltage. I think that next year I will make a point of always writing the gain equations as $V_{out} - V_{ref} = g(V_{p} - V_{m})$, so that the output is always a difference between two voltages, rather than as $V_{out} = V_{ref} + g (V_{p} - V_{m})$, like I’ve been doing this year.  Although the two statements are algebraically the same, I think that they’ll be better able to do multistage gain computations and less likely to forget to connect up Vref if they have the output expressed as a difference.
• I cleared up some small misunderstandings of how to do layout on the protoboard PDF drawings.

At the end of class I collected all the homeworks, and I “graded” them tonight.  I’m providing feedback and a done/not-done check, not a grade (which is lucky for them, since most were such sloppily done notes that I doubt that most of the students could reconstruct their thoughts from the notes).

I did get a chance to introduce the students to pulse-width modulation and FETs today, which are essential topics for the class-D power amp next week, but I’m not happy with the presentation I gave—I did a better job in the handout, which I suspect most of the students will never read.  The problem with working so much this weekend was that I was very tired all afternoon today, and was not able to put together as coherent a presentation as I wanted to.

I still have to do a design for the class-D power amp with the new comparators, but I’m too tired to do it tonight.  I’ll probably sketch it on paper tomorrow and do a neat schematic in SchemeIt tomorrow night. I’ll wire up all I can at home either tomorrow or Wednesday night, while waiting for the comparator chips and MCP6004 op amp chips to arrive.  (Actually, I’ll probably just use an MCP6002 chip, since I don’t need 4 op amps, and I still have a couple of MCP6002 chips left.)

Tomorrow I need to remember to bring in the cheap aquarium air pump, some tubing, and a clamp so that students can observe back pressure and the fluctuations in pressure from the pump (assuming that they get their amplifiers working).

2014 May 18

Problems rewriting the Class-D amplifier lab

Filed under: Circuits course — gasstationwithoutpumps @ 13:49
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I was trying to rewrite the lab handout for the class-D amplifier yesterday, and I ran into some problems. We were unable to get the same nFET and pFET as last year (at least one of them has been discontinued by the manufacturer), so I ordered other cheap MOSFETs this year.  I was going to check out the circuit to make sure that the new FETs worked before the quarter started, but I got swamped with other things and never got around to it.  In looking over the specs for the FETs and doing some calculations for the handout, I realized that new nFET (AOI518) has a large input capacitance (about three times as large as last year’s nFET NTD5867NL-1G), and so turning it off with the open-collector output of the comparator chip we bought (LM2903 dual comparator) is likely to be too slow, even with careful design of the pullup resistors.  It was tricky enough last year to keep the shoot-through current short enough to avoid heating the transistors too much.  It probably doesn’t help that the pFET we’re using this year (IRFU9024NPBF) has a small gate capacitance, and so can be turned on quickly.  We will have one transition with almost no overlap (pFET turning off, nFET turning on), and one with a large overlap (pFET turning on, nFET turning off).

I’m a little confused by the data sheets, because the input capacitance seems to vary much more between FETs than the gate charge does, so I’m not sure exactly what the input capacitance means.  For example, at VGS of 4.5v, the total gate charge of the AOI518 is typically 8.8nC, while for the NTD5867NL it is 7.7nC, a much smaller ratio than the 1187pF vs 675pF for ICSS. If the gate charge is really what matters (and I think it is), then we may not be in as big a trouble as I feared, though we still have problems with how long it takes to turn off the nFET.

The design we used last year had pullup resistors for the open-collector comparator output, which drove the FET gates directly:

Class-D output stage using comparators driving the FETs directly. [Updated 2014 May 19—I had the pFET source and drain swapped.]

Note that the equivalent circuit for the open-collector outputs has an impedance that is essentially the pullup resistor for both pulling up and pulling down, and Rn needs to be made fairly large in order to ensure that the nFET is turned completely off. This means that the RC time constant for discharging the nFET gate is quite large and so the nFET is turned off slowly. If we limit the power supply to ±7v and the current to 1A, we have a 14w peak power and 7w average power during the turn-off time. If the PWM frequency for the amplifier is about 50kHz, then the period is 20µs, and a turn-off time of 1µs would result in dissipating 350mW in the nFET. That’s not too bad—at 50°C/W junction-to-ambient, it is only a 17.5°C temperature rise (of course, that thermal resistance assumes that the transistor is on a copper pad on a PC board, not sitting in a breadboard). But if the turn-off time is 2µs and the PWM frequency is 100kHz, we’d have 1.4W dissipated and a 70°C temperature rise, which won’t damage the transistors, but may make them hot enough to melt the plastic on the breadboard or burn someone’s finger.

Last year, by using the two comparators in the package to drive the pFET and nFET separately, we could just barely get the nFET shutoff to be fast enough. The problem of choosing appropriate pullup sizes is fairly tricky, especially as the students have not seen any models of FETs and have no notion of the Miller capacitance and gate charge. I gave them a bunch of gnuplot scripts to try to plot out what the effect of various choices would be, but it ended up being mainly cut-and-try work, fiddling with the resistor sizes and the power-supply voltage to keep the transistors from getting hot. I was trying to simplify the pullup design part of the lab yesterday when I ran into the problem that the new nFETs may be slower to turn off than last year’s and that there may not be a reasonable design point for the students to find.

I’ve been struggling with finding a workaround that I can test in the next week, while teaching the students about class-D amplifiers and supervising their pressure-sensor instrumentation amp labs. Here are the ideas I’ve come up with so far:

• Try the same basic design as last year, and see if I can get a power supply voltage and pullup resistor settings that work.  I’ll have to do this in the lab on campus, because I don’t have a power supply at home that provides the same voltage ranges.
• Replace the AOI518 nFET with one that has a lower input capacitance, such as the PSMN022-30PL,127.  The gate charge at VGS of 4.5v is 4.4nC, about half that of the AOI518.
• Replace the open-collector comparator with one that has push-pull output, like the TLC3072, which can provide ±20mA current (more than the LM2903, even before we allow for the current through the pullup resistor).
• Add a driver chip that is intended for driving a pair of FET transistors, like the FAN7382, which can provide very fast rise and fall times even into 1000pF loads. But the driver chips are intended for two nFET transistors, and the charge pump for the high-side driver would be difficult to explain in this course and requires external components (diodes, resistors, and capacitors) that the students would have no idea how to choose.
• Use an H-bridge or half-H-bridge chip instead of having students design the power stage with FETs.  Most are designed for controlling motors, and don’t give timing specs that would tell me whether they could handle a high enough PWM frequency for audio output.

Currently I’m leaning towards using the TLC3072 comparator.  Eliminating the pullup design simplifies the design process for the students, and the 20mA capability should be able to discharge the gate charge sufficiently fast.  The data sheet claims rise and fall times for a 1000pF load as 250ns and 150ns (for a 5v signal—it is not clear how the rise and fall times change with power-supply voltage, though I’d expect a roughly linear relationship).  So for a 16v power supply (the largest allowed), the fall time for driving the AOI518 gate might be as much as 1µs, which should be fast enough.  We could even add a resistor from the AOI418 gate to its source, to pull the transistor off faster at the cost of not turning it on as fully or as fast.

I think I’ll order some TLC3072 chips and some PSMN022-30PL,127 nFETs, so that I should be able to make a working class-D amplifier this week.  There isn’t time to have the lab staff order stuff, so this will come out of my pocket. I’ll have to order the parts today in order to get them in time to test the circuit before the class has to do the lab a week from Tuesday.

I’m also going to be late getting the lab handout to the class, since I’ll want to test the circuit before finalizing the handout.  I really wanted to get the handout to the class tomorrow, since we’ll be covering class-D amplifier principles in lecture tomorrow.  I might end up doing what I did last year—giving a handout on time and handing out an addendum later with updates.

The time spent yesterday on this lab handout has put me way behind schedule—I still haven’t done the grading for the weekend nor written up the quiz for Wednesday’s class. I missed going to see the broadcast of the National Theatre of London’s production of King Lear on Thursday because of lab running so late, and I missed the rebroadcast this morning, because of being so far behind on the work for the course. Oh well, I’m depressed enough about the problems I’m facing with the lab that seeing something as bleak as King Lear would probably not have been good for me.

2012 December 21

FET threshold tests with Bitscope

Filed under: Circuits course — gasstationwithoutpumps @ 22:51
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Some of you may recall my complaining about the lack of USB oscilloscopes for the Mac a couple of years ago, when I bought myself a used Kikusui COS5060 analog oscilloscope.  In the comments for my complaint post, someone named Chris had recommended last March that I check out bitscope.com, as they supposedly had software for the Mac OS X.

This year for my birthday, I bought myself the Bitscope Pocket Analyzer, a tiny (6.6 × 6.2 × 1.7 cm) USB attachment that can act as a 2-channel oscilloscope, plus a few digital channels, plus a waveform generator. The price is a little high (about \$300) and it was a hassle to buy, because my credit card company was convinced that a transaction from Australia had to be fraudulent, and didn’t get around to checking with me for a couple of days, after rejecting the purchase three times.  Luckily the bitscope people were very nice about it and even gave me free faster shipping, which was very generous, as none of the delays had anything to do with them—just with my miserable excuse for a bank (I’m looking at you, Wells Fargo!).

The bitscope does have software for the Mac OS X, which is appropriately labeled as beta-release software.  There are still bugs in it (for example, when I try to save a screen shot in jpg format, it saves it in png format instead), but most of the functionality one would want is there. Saving also only saves the main scope display, not all the setting displays around it (so there is no record made of most of the settings, and any cursor readings have to be manually recorded, or you use the screen-shot features of your operating system).  The value displayed on the screenshot that is saved is the “bias” or mean waveform voltage—perhaps the most useless of the measurements they could have chosen to make the displayed one. There are probably other bugs, but I’m still unfamiliar enough with the controls that I usually can’t tell when I’m making a mistake vs. when the software is.

Like other digital scopes, the Bitscope records a full frame before displaying anything, and it alternates a frame of channel A with a frame of channel B.  This can be rather disconcerting if you are using a slow time base (like for an EKG signal), as nothing appears on the screen for a few seconds after the trigger.  With higher speed time bases, the frame rate is fast enough that the delay is not noticeable.

Also like other digital scopes, the controls are highly idiosyncratic and difficult to learn.  In the case of the bitscope software, the controls are even more idiosyncratic than usual—they have something they call “Act on Touch” controls, which behave differently depending where on the button you click:

click and drag up and down or left and right on a parameter to adjust its value. Click on the left or right edge of the parameter to select a previous or next value.

Right-click (or control-click on a Mac or press-and-hold on a tablet) to pop up a context menu and double-click to open an editor to type in a value or select a default value.

Note that the cursors cannot be adjusted by this “Act on Touch” method nor with the arrow keys, but can only be dragged on the image, which makes measuring some parameters more difficult that in needs to be.

I did eventually manage to do some plots that correspond to the taking the thresholds of a pMOS field-effect transistor (pFET) and an nMOS field-effect transistor (nFET).

Test circuits for determining thresholds of the FET transistors. I only hooked up one of the test circuits at a time (nFET or pFET), not both at once.

Results for testing the NTD2955 pMOS FET. I set the cursor about where the transistor turns on, at 2.08V, which gives a threshold voltage of 2.08V-4.93V= -2.85V, close to the nominal -2.80V, and well within the specs (-2.0V to -4.0V).
I see that I ended up with non-standard vertical scaling here for channel A (the Vp voltage).  Changing the range of the inputs picks non-standard scaling by default (another stupid choice by the software designers).

The curve clearly shows the quadratic dependency of the current on the gate voltage above threshold.  With a little more care in using the bitscope, I can see that I get 1v (100mA) when the voltage is 1.56v (so -3.37 relative to the source), which would give me something like I= 370(2.85V+VDS)2 mA/V2.

I also did a similar plot for an nMOS FET:

Bogus threshold plot for NTD5867 nMOS FET.   The current does not seem to follow a quadratic curve above the threshold voltage, because the 5.2V range on Channel A is truncating part of the curve (which goes from -2.6V to +2.6V, not 0V to 5.2V).

The current for the nFET peaked at almost 500mA, which is a 2.5W power dissipation: far more than the lowly ¼W resistor could handle even for a short duty cycle. I had to pull the power wire from the breadboard quickly after each test, to keep from burning up the resistor. I did not repeat this test with a 10Ω resistor, but switched to a 100Ω resistor for safety. If I have the students measure the thresholds for their FETs, I’ll have to make sure they compute the minimum resistance value that they can safely use with the voltage they are testing at, and not just blindly grab a convenient size that was sitting around on the benchtop, as I did.

With a 100Ω series resistor, I detect the nFET turning on at 1.66V, and see the expected quadratic dependence of the saturation current on gate voltage above threshold.  The 1.66V is not close to the nominal 1.8V threshold, but is within specs (between 1.5V and 2.5V).

The 100Ω resistor does not get warm, as the 0.25W max power dissipation times the approximately 1/3 duty cycle is well within the ¼W power limit.  Using a larger resistor makes the threshold detection a little easier, since turning the transistor on only a little to get 1mA of current, provides an easily seen 0.1v swing.

At a gate voltage of 2.08V (0.42V above threshold), the output current is 40mA, so the saturation current is about 227(VDS-1.66V)2 mA/V2.

Now that I’ve characterized the FETs, I should probably try designing a power amp using them. I tried several designs this morning in CircuitLab, but the circuit lab simulator has serious problems with op amp circuits. It gets confused by the feedback loops and neglects to bound the voltage values, so I was getting DC “solutions” with outputs in the teravolts. It would be quite a trick to get a teravolt output from an op amp with a 5v power supply!

Some of my designs were quite clever—one that I was curious about used DC coupling throughout, but automatically compensated for the DC offset of the microphone and should keep the voltage across the speaker centered without needing a dual-rail supply (that is, no high-current center supply) nor large DC-blocking capacitors. It took 4 op amps and a differential amp, though, so was not a cheap solution (if it even works—I’ll have to wire it up to find out, as the simulator couldn’t handle it).

I think I’d better try a couple of straight-forward designs and see how they work, first—designs the students are more likely to come up with.