# Gas station without pumps

## 2016 March 31

### Pep talk for students frustrated at the end of the first week

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 20:48
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Some of the students in my Applied Electronics for Bioengineers course are feeling frustrated at the end of the first week (often due to imposter syndrome, not any real inability to do the work).  I sent them the following e-mail this evening:

To the class—a number of people are feeling overwhelmed, because of the wide range of preparation that people in the class have had.  This is supposed to be a first course in electronics, but a number of people are taking it after having had other electronics courses.  If the advanced students are allowed to dominate the questions in class, I’ll never know what help the students with less preparation (that is, the students the course is intended for) need.  If you are feeling overwhelmed or out-matched in class, please ask questions!  I know that there are people feeling like they need more help, but I don’t know exactly what help they need.
I could guess at what is causing people problems, but I’m likely to guess wrong, and I don’t want to waste a lot of time on reviewing stuff that everyone in the class gets, while not spending any time on the stuff that is really needed.
In short, I’m saying that I need a lot of questions from people in the bottom quarter of the class, and I don’t think I’ve been getting them.
Going to [the group tutor]’s sections is another way to catch up to those you perceive as being ahead of you.
It looked to me like everyone pretty much got labs 1 and 2 done, and that most of the class (though perhaps not everyone) had a decent grasp of aliasing.  A bigger fraction of the class had PteroDAQ and gnuplot installed and working by Lab 2 than in any previous offering of the course—so this looks to me like a very promising start to the quarter—it may have seemed chaotic to you with not all the parts arriving on time and last-minute patches to PteroDAQ to compensate for changes in laptop operating systems, but these startup pains are normal—I expect to have them every time the course is offered.
Lab 2 was much harder than intended this year, because of the resistor assortments not including 470kΩ resistors, and I was impressed by how the class rose to the challenge, despite not having had the lectures yet that would really support the design work done (those are scheduled for week 3, I believe). I’m going to have to rewrite parts of Lab 2 to allow for the possibility of not having the right parts available.
The deal with Lab 2 was this: I had given them in the book a circuit to build that consisted of a function generator, a capacitor, a pair of resistors, and the Teensy board with the PteroDAQ software. The idea in terms of skills was for them to learn how to lay things out on bread board, collect data with PteroDAQ and do some minimal plotting with gnuplot.  The concept they were supposed to be learning about was aliasing, which I was planning to cover in lecture yesterday, but I got diverted to other equally important topics.
The problem was that the design I gave them could not be implemented, because the resistor assortments (which only arrived yesterday, so I had no idea exactly what resistors would be in the kit) did not have the specified 470kΩ resistors!  I probably should have redesigned the circuit for them and had them build a different circuit which would have worked equivalently (like using 1MΩ and 4.7µF instead of 470kΩ and 10µF), but I did not know what resistor values they did have in their kits.
Instead, on the spur of the moment, I chose to have the students come up with a design themselves that has the same (or nearly the same) RC time constant as the circuit in the book.  If I’d had an hour to think about how to handle the challenge, I might have chosen a different approach. The assignment I gave them tied in well with yesterday’s unplanned lecture—without that lecture, I would not have considered them capable of redesigning the circuit.
I think that everyone in the class did come up with a design that let them do at least a few recordings with PteroDAQ, though they did not get as much time to explore aliasing as I had originally intended. There were several different designs students came up with, including the 1MΩ and 4.7µF design, 10MΩ and 0.47µF, putting two 1MΩ in parallel to make 500kΩ, and building the 470kΩ out of a series chain of resistors.
Having a real design challenge for this first lab was in one way a good one (it had bothered me that there was no design element in the first week of lab), but this design challenge was too much for the first week.  After lab some students were feeling overwhelmed and wanting to drop the course—even though this year’s class is well ahead of previous year’s classes (even the students who are struggling are further along than their counterparts in previous years).
Now my challenge is to convince the students who are feeling stretched to stick with the class for another week or two, so that the lectures can catch up to what they need to know and they can have a more confident base to work from.

## 2015 July 25

### Noise from PteroDAQ KL25Z

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 15:31
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In a series of posts (most recently More on measuring PteroDAQ KL25Z input impedance), I’ve been measuring the input impedance of my various ways of measuring AC voltage, and having some trouble getting a reasonable value for using the PteroDAQ as a measuring device.  In the most recent post, I noted that hardware averaging seemed to make the measurements worse, not better, when the input impedance was high.

I decided to map out how bad this measurement error was, by changing the source resistance and seeing how the voltage measurement changed. I picked a low frequency (55Hz) with a high sampling rate (6001.5Hz), so that aliasing was not an issue.

The voltage measurements are fine up to a source impedance of 10kΩ without averaging, but only to 1kΩ with 32× hardware averaging.

My conjecture about the problem with the 32× averaging was that the KL25Z sample-and-hold circuitry was injecting interference onto the pin, and that too high a source impedance did not provide sufficient current to eliminate this noise before the next sampling of the pin.

I tried fixing the problem by adding a small capacitor between the pin being measured (PTE0) and ground. The idea is that the capacitor can short out the high-frequency interference, using charge from the capacitor to cancel the noise rather than from the source. If the capacitor is too large, then the low-pass RC filter of the source impedance and the capacitance will reduce the signal, but if it is too small, then the sample-and-hold will be confused by the noise from the previous sample. With the 55Hz signal and a 100kΩ source impedance, I tried a number of capacitors, looking for the one that would maximize the voltage reading with 32× hardware averaging. I settled on 470pF, which would give a corner frequency of 3.39kHz (approximately my Nyquist frequency).

Putting in a 470pF capacitor to bypass the noise from the sampling helps when there is no averaging, but not so much when there is averaging.

With the 470pF capacitor, the source resistance can get as high as 100kΩ before the noise injection becomes a problem, when not using hardware averaging (at the 6kHz sampling rate—higher sampling rates would start seeing problems at lower impedances. In general, I think that sampling period should be at least 3.5 times the RC time constant of the source resistance and the added capacitance. For single-ended, 16-bit measurements with short sample times, the KL25Z hardware averaging has a period of 25 ADC clock cycles and PteroDAQ is set up to use a 6MHz ADC clock, so the samples are at 240kHz, which would suggest a maximum source impedance of 2.5kΩ for a 470pF capacitor using hardware averaging. This seems consistent with the measured data.

I realized this morning that I did not need to just conjecture the noise on the pin—I could stick an oscilloscope on it and measure it. I used a 47kΩ series resistor (so that the 1MΩ || 10pF load of the Bitscope oscilloscope would not make a huge difference) and a 10 Hz input from the FG085.  I set the PteroDAQ sampling rate to 3750Hz, so that there would be about equal time for the 32 samples and for recovery between them.  I captured single traces and got fairly consistent results.  Here is an example:

This trace at 50mV/division and 20µs/division shows the 240kHz noise from the sample-and-hold circuitry for the first half, and the much smaller noise when not sampling for the second half. This trace was done without the 470pF capacitor.

The noise injected by the sample-and-hold circuitry is about 190mV peak-to-peak with the 47kΩ resistance, or about 4µA.

Adding the 470pF capacitor reduces the peak-to-peak noise to about 16mV or 340nA, but there is enough of a bias to the noise that the error is much larger, as seen by the slow decay back to the correct value in the following trace:

At 10mV/division and 20µs/division, this trace shows both the reduction in noise from using a 470pF capacitor and slow recovery to the correct voltage at the end of the 32 samples. The time constant for 470pF times 47kΩ is about 22µs, about 5.3 times the sampling rate (or about 20 times longer than desirable for accurate reading).

The injection of noise back into the circuit being tested is a particularly nasty property for test equipment to have. One could avoid it by adding a unity-gain buffer before the pin, which would have three good effects:

• The input impedance would now be the impedance of the op amp, which can be in the 10GΩ range (for the cheap MCP6004 op amps we use in class)
• If there was noise from the microprocessor, it would not be injected into the circuit being tested.
• The source impedance for the analog-to-digital converter would now be around 40Ω (for the MCP6004 op amps), so all these noise problems would go away.

There is one downside to using a unity-gain buffer: you get some non-linearity near the power rails, so the range of useful operation is reduced somewhat.

So when using the PteroDAQ, it is important to pay attention to the source impedance.  When the source impedance, R, is high, one can either

• add capacitance to reduce the switching noise of the sample-and-hold circuitry (resulting in an RC time constant >3.5 times the sampling period, which can be user-specified (no averaging), 4.1667µs (single-ended channels), or 5.6667µs (differential channels) on the KL25Z; or
• add a unity-gain buffer to separate the input from the pin.

The noise consideration is a bigger constraint on operation than the input impedance of the analog-to-digital converter pins, which made my attempts to characterize the input impedance somewhat quixotic.

## 2015 July 21

### Measuring PteroDAQ KL25Z input impedance

In a series of posts (most recently Measuring BitScope BS-10 input impedance), I’ve been measuring the input impedance of my various ways of measuring AC voltage:

meter Z
DT-830B 0.42MΩ || 31.59pF
DT-9205A 13MΩ || 22pF
BitScope BS-10 oscilloscope 1.025MΩ || 9.8pF

I spent yesterday trying to add the PteroDAQ data acquisition system with the Freedom KL25Z board to that list.

One problem was that PteroDAQ was not designed to report an RMS voltage, but just a waveform, so I modified PteroDAQ to report the mean and standard deviation of a channel (not in the released version yet, as I still have some work to do on the user interface). Note that the mean of a channel is its DC bias, and the standard deviation is the RMS AC voltage. (I’ve never much cared for meters that report RMS AC+DC, which is the root-mean-square voltage without separating AC and DC components.)

A bigger problem is that PteroDAQ can only sample at fairly low frequencies, but the parallel capacitance is expected to be fairly small (pin capacitance for the pin is only about 7pF and the short wiring on the board should only add another couple of picofarads), so the RC time constants will be small. The result is that the low frequencies below the Nyquist frequency will not be much affected by the parallel capacitance, and all I would be able to estimate is the DC resistance of the inputs.

I can take advantage of a trick, however, to get effectively much higher sampling rates: aliasing. Because the input is a sine wave of stable frequency, f, I can sample it at every $\frac{n+\phi}{f}$ seconds and get a waveform that advances by phase $\phi$. I can pick the integer n to be large enough to get a feasible sampling rate while still seeing the whole waveform, especially if I pick the phase advance to be about $\phi=\pi/128$, so that I see all the 256 entries in the function generator’s table.

This trick has the further advantage of presenting the sample-and-hold with about the same value as it sampled on the previous sample, so that I don’t have to worry about the short sampling time not getting fully charged through a high-impedance input.  If I don’t do the aliasing trick, then the short sample time PteroDAQ uses (4 cycles of a 6MHz clock, or 667ns) is not enough to charge the sampling capacitor to the final voltage.

At higher frequencies, even this short sampling time is too long—at 1MHz the voltage changes substantially in 667ns, and the sampling capacitor ends up averaging the value over the sampling interval, which reduces the AC RMS voltage.

I made my measurements with the hardware averaging set to 1×, since averaging multiple readings is a digital low-pass filter that would hide the analog low-pass filter I’m trying to measure.  Because the measurements at 1× are so noisy, I took a large number of  measurements to determine the mean and standard deviation.  The results are still a bit noisy, as I did not realize the importance of having very precise sampling rates initially—if the $\phi$ value is too small, then I have to be careful to include an integer number of periods of the aliased waveform in the averaging to avoid bias, and if it is too large, then the short sample time is not long enough to charge fully and my waveform is not full scale.  A good compromise seems to be to pick n so that the sampling rate is around 5kHz and $\phi=\pi/128$ to get about a 19.5Hz aliased waveform. Only a few of my measurements were done with these settings, so I should probably redo the whole set at some point.

The aliasing trick is not a perfect one—at high frequencies there are a lot of glitches, where it is clear that the sampling did not happen at precisely the place in the waveform desired. This is probably due to jitter in the digital phase oscillators used in FG085, as the PteroDAQ interrupts should come at precise intervals (though the intervals may not be at exactly the frequency desired). The noise is much more of a problem with a high impedance source, as it may take several samples for the sampling capacitor to get back to the correct value.

I measured PTB0 with 1× sampling both directly driven by the FG085 (with 2.9Vpp and +1.8V offset) and through a 100.1kΩ resistor.

The dropoff in voltages at high frequencies with not series resistor is probably due to the averaging of the 667ns sampling time.

The impedance estimate derived from these measurements is pretty solid on the DC resistance, but the parallel capacitance estimate varies depending on how much of the high-frequency measurement I use in the fitting.

My estimate of C is 8pF±2pF, depending on how much of the high frequency data I include in the fit.

Estimating the input impedance of the single-ended pins of KL25Z at 2.5MΩ || 8pF seems pretty good. I’ll have to check the differential inputs separately, as there is no reason to suppose that they have the same input impedance.

I think that the 8pF I’m seeing is mainly the pin capacitance of the PTB0 pin, with a little extra board capacitance. The sampling capacitor is not really measurable here, since it is only connected to the input for very short intervals. To measure the RC time constant of the sample-and-hold circuit, we’d have to vary the sampling time (which is possible on the KL25Z, but which PteroDAQ is not set up to do).

## 2015 April 2

### Moving sampling lab early was a good idea

Filed under: Circuits course — gasstationwithoutpumps @ 20:00
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This year I moved the sampling and aliasing lab to the first week, from the middle of the quarter.  To do this, I had to remove the design component from the lab: I gave them the circuit for the high-pass filter that re-centers the function generator output halfway between the power rails.  I didn’t tell the students that the function generator has the ability to set a DC offset itself, so we could have done the observations without building the filter, because a big point of the lab was to get students to translate a schematic into components and wires on a breadboard.  I was worried that the lab would not make sense before we’d covered RC filters, but by treating the filter as “magic” to be explained later, we could concentrate on the lab skills of wiring and running the PteroDAQ software, without them having to figure out a design at the same time.  The rest of the quarter will all be design labs.

I started the lab class with a mini-lecture covering:

• block diagram.  I constructed a block diagram starting from the two ends: the function generator and the PteroDAQ, and working out what was needed in the middle to make the output of the function generator match the input of the KL25Z analog-to-digital converter in the PteroDAQ.
• schematic. I redrew the schematic from my book:

The DC-blocking filter they built has a corner frequency of 0.03Hz, and they were looking at waveforms in the 1Hz–25Hz range.

I explained briefly how capacitors block DC but allow AC currents, how electrolytic capacitors work, and how the insulating layer self-repairs when the voltage is in the right polarity and how it can catastrophically fail with the polarity reversed.  (I did mention blowing up capacitors.)  I did not explain RC time constants, high-pass filters, or even voltage dividers, promising that all the theory for this circuit would be coming over the next two weeks.

• resistor color codes. I did not give the full resistor color code, but just explained the red-red-orange-gold bands on the 22E3Ω±5% resistors we had.
• breadboard layout. I explained what holes were connected to what on the breadboards, and why the central channel was there (for dual-inline packages, which also dictate the 0.1″ spacing).
• black/red color convention. I insist on students using black for GND and only for GND, and using red for the positive power rail (3.3V in this case) and only for the positive power rail.  I handed out about 4″ each of red, black, blue, and green 22-gauge wire to each pair of students.  (The lab has a couple of big spools of white and orange 24-gauge wire, but I’ve found 24-gauge unreliable in breadboards, so we’re going to use small amounts of 22-gauge instead.)
• plotting two channels with gnuplot.  The assignment called for plotting the same signal twice, once at 50Hz and again down-sampled 10× to 5Hz), so I needed to show them how to plot both on the same plot in gnuplot (plot “data.txt” using 1:2, “data.txt” using 1:3 ).
• V always relative to ground.  I reminded students that voltage is always the difference between points, and when we talk about the voltage at one node (like at the input), we always mean relative to the special node we call ground.
• SchemeIt to create schematics.  I suggested to students that since the report this week is primarily about learning to use the tools they’ll need all quarter, it would be best if they reproduced the schematic using SchemeIt, rather than just cutting-and-pasting from the book.
• function generator and oscilloscope demo. I demonstrated the use of the function generator and told them about the peak-to-peak voltage being a deliberate lie and needing to double what the function generator claims the output is (since we don’t use the expected 50Ω load, but an effectively infinite resistance).

After the mini-lecture, I had the students set up the function generators and observe the output on the digital oscilloscopes.  They also built their circuits, which I inspected before they powered them up.  There were the usual confusions about what holes were connected, but they seemed to clear up faster than usual this year.  For the morning lab, I had not mentioned the “V relative to ground” convention at the beginning of class and had to do a very short mini-lecture in the middle of class.  Perhaps because I made notes on the board of everything I ended up covering in the first lab, the second lab went a lot smoother.

I did find out this evening that one group had not read the assignment properly and missed the whole point of the sampling and aliasing lab—they only recorded one channel of data, not two at different sampling frequencies.  They’ll borrow correct data from another group (with appropriate credit).  I hope that the other group put appropriate metadata in the notes, so they can figure out what they are looking at.  I also hope that finding out at the last minute that they’d done the lab wrong will induce the students to read the assignments before lab in future, when the stakes are higher.  I am requiring pre-lab homework to be turned in on Mondays starting next week, so there will at least be a deadline before lab for them to have done some of the reading and thinking.

The students still have not gotten their full parts and tools kits.  They got breadboards and electrolytic capacitors today—we only loaned the 22kΩ resistors, since the resistor assortments have not arrived yet.

I was in the lab essentially all day 9:45—17:45, except for a break to eat my lunch just outside the lab between the two lab sections.  During that time I helped a lot of the students with installing the software they needed.  Incidentally, the widened hallway outside the lab is a popular study spot for engineering students (there are frequent formal and informal group study sessions there)—the area has been informally named “Jack’s Lounge” after the picture of a generous donor at the entrance (Jack Baskin, after whom both the building and the School of Engineering is named).  I don’t know if the implication is intended to be that Jack’s idea of “lounging” is studying hard, but if so it is rather flattering to him.

Next week’s lab will probably require more of my time, as they involve the temperature measurements, and I have to set up the hot water urn and ice water well before class starts.

## 2015 April 1

### Second lecture in Spring 2015 electronics

Filed under: Circuits course — gasstationwithoutpumps @ 21:38
Tags: , , , , , , ,

The lecture today started by me redoing the demo that failed on Monday, showing them how to run PteroDAQ and display the results with gnuplot.  Everything worked fine this time. I even showed them the use of two channels, by putting the Bandgap voltage reference (1v) on the second channel, and plotting its variation over time:

The ADC was measuring consistently slightly low (probably because the power supply voltage had drifted a little) from when PteroDAQ measured the bandgap reference to set the calibration).

I showed them how to plot the signal divided by the bandgap signal to correct for such calibration problems.  The plot also gave a good segue to talking about resolution, precision (which I equated with repeatability), and accuracy, because the step size of about 50µV for the ADC is clearly visible (3.3V/216), but the signal is not repeatable to 50µV.  The precision is limited to about ±200µV and the inaccuracy can be as much as 700µV.

I then walked them through a gnuplot script for demonstrating sampling:

# frequencies in Hz
sine_freq = 1.100 *1.0
sample_freq= 40. *1.0

sine_wave(t)=sin(2.*pi*sine_freq*t)
sampled(t) = sine_wave( floor(t*sample_freq+0.5)/sample_freq )

set title sprintf("Sine wave of %.2fHz, sampled at %.2fHz", sine_freq, sample_freq)
set xlabel "time [seconds]"
set ylabel "signal"

set samples 5000
set yrange[-1.05:1.05]
set xrange [0:2]
plot sampled(x) notitle, sine_wave(x) lt 3 notitle


which produces a simple example of discrete-time sampling:

Sampling a 1.1Hz signal at 40Hz does a good job of representing the waveform.

I even explained why I used “lt 3” for making a red/blue color distinction rather than a red/green one (around 5–7% of males have some form of red-green color blindness).

I then showed them the effect of changing the sampling rate (by alternating “sample_freq=…” and “replot” commands). I think that this will help them with tomorrow’s lab, in which they use the function generators in the lab to generate sine waves, and look at them with PteroDAQ software on the KL25Z boards.

Speaking of PteroDAQ, one of the students in the class and I figured out what was going wrong on the Mac OS 10.10.1 installations of PteroDAQ. It turns out that the problem was not specific to the OS 10.10.1, or even to Macs, as we observed the same problem of not being able to select a port (because the GUI automatically deselected it) even on a Windows 7 box.  It turned out to be a problem in Python 3.4.3 (the latest release on python.org) not playing nicely with Tkinter.  Rolling back to Python 3.4.0 fixed the problem (with either Tcl/Tk 8.5 or 8.6).  We’ve not yet looked to see whether 3.4.1 or 3.4.2 work correctly.

The rollback to Python 3.4.0 worked on both Mac OS 10.10.1 and on Windows 7.  The only machines we haven’t yet gotten a demonstrably working PteroDAQ installation are Windows 8 machines—the problem there seems to be installing drivers for the USB port.  The Arduino community has encountered the same problem (Windows 8 insisting on digitally signed drivers) and the community figured out how to turn off that insistence. The instructions there (http://forum.arduino.cc/index.php/topic,94651.msg727588.html#msg727588) are rather scary.  A more tutorial presentation is given by SparkFun at https://learn.sparkfun.com/tutorials/disabling-driver-signature-on-windows-8

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