In a series of posts (most recently Measuring PteroDAQ KL25Z input impedance), I’ve been measuring the input impedance of my various ways of measuring AC voltage:
||10.87MΩ || 18.54pF
||0.42MΩ || 31.59pF
||13MΩ || 22pF
|BitScope BS-10 oscilloscope
||1.025MΩ || 9.8pF
|PteroDAQ KL25Z single-ended
measured with 100kΩ
|2.6MΩ || 8pF
Last night and today, I’ve been struggling with trying to measure the input impedance of the differential inputs (spoiler: the problems had nothing to do with inputs being differential). I set the KL25Z board up so the PTE20 was the signal from the function generator, and PTE21 was the output of a voltage divider from the 3.3V power (about 1.9938v). Because the estimated input impedance for a single-ended channel was 2.6MΩ || 8pF, I started by measuring the voltages for adding 0Ω and for adding 3.3MΩ in series using the same aliasing tricks to measure high frequencies as in the previous post:
Here was my first WTF moment: why did the voltage readings drop essentially to 0 around 44kHZ, and then go back up?
The behavior of the voltages with no series resistance mystified me for quite a while. Where was I getting that nearly perfect zero around 44kHz? How did the cheap differential amplifier in the chip produce such a near-perfect zero? I was convinced it was from the differential amplifier, because I saw no zero at 44kHz for a single-ended input.
It took me a long time to realize that I had been measuring with the 4× averaging turned on (the default), rather than the 1× averaging that I had intended. The 4 samples being averaged are essentially a low-pass, finite-impulse response filter with the transfer function , with a sampling rate that is the time between the samples set by the hardware averaging. That transfer function has zeros corresponding to ¼, ½, and ¾ the sampling rate. For 16-bit differential measurements, there are 34 cycles for each sample, which at 6MHz gives a hardware sampling rate of 176470.59Hz, and ¼ the sampling rate is 44117.65Hz, right where I was seeing a zero.
So the first mystery was solved: what I was plotting for the no-resistance case was the response of the averaging filter:
The FIR response of the averaging filter is a very good fit to the observed data for the no-series resistance voltages.
I decided to use the data before the cutoff of the averaging filter to get an estimate of the input impedance:
At 155kΩ || 760pF, this input looked like a lot lower impedance than the estimates I’d made for a single-ended input—so much so that I had trouble believing in such a low input impedance.
Since the 4× averaging limited the high-frequency response, I redid the measurements with 1× averaging:
With no hardware averaging, the voltage data looks usable out to 100kHz.
I did the impedance estimation as before by fitting to the voltage ratio seen with the 3.3MΩ resistor and with no series resistor:
With no averaging I get a very different input impedance than with 4× averaging!
I was very surprised to get a different estimate for the input impedance with no hardware averaging: from 155kΩ || 760pF with 4× averaging to 900kΩ || 440pF without averaging. I was particularly mystified by the change in the low-frequency resistance, as measurements of 5Hz signals should not be seeing changes from differences in averaging.
Since I had already been fooled once by thinking something was due to the differential amplifier, when it was actually something else, I decided to check what the single-ended input (just PTE20, rather than PTE20-PTE21) was doing at a single frequency (55Hz) with the 3.3MΩ series resistor:
I tried a number of different sampling frequencies, to see if there was a problem with my understanding of the effects of aliasing. Aliasing made sense to me, but the decreasing amplitude with more averaging did not.
I got pretty much what I expected in terms of the effects of sampling frequency. Being just a little off from the input frequency gave me about the same results as if I heavily over-sampled the waveform, but I got considerably attenuated results from using a sampling frequency near a small multiple of the input frequency as the samples had wildly different values from the preceding sample, and the sample-and-hold circuit didn’t have a long enough sampling time (667ns) to converge.
The weird behavior that confused me was the reduction in RMS voltage as hardware averaging increased. I only saw this behavior with the 3.3MΩ series resistor, not with direct connection of the function generator to the pin.
The datasheet for the KL25 processors does warn against using high-impedance sources for the ADC inputs, especially with short sampling times, because the sampling capacitor needs time to charge. They also suggest adding a 10nF capacitor to the inputs when the source impedance is high—then the sampling capacitor shares charge with that input capacitor, rather than having to be charged through the high-impedance source. With a 3.3MΩ source, a 10nF capacitor would provide a corner frequency of 4.8Hz—lower than most of the signals I’m interested in measuring.
But the limitations on the charging of the sampling capacitor are worth thinking about. The pin capacitance that is present just as parasitic capacitance is on the order of 6–20pF, for an RC time constant around 20µs–70µs with the 3.3MΩ source. But the interval between hardware averaging samples is 25 (6MHz) cycles, only 4.167µs. So if the sampling adds noise to the input pin (perhaps capacitive coupling from the gate of the sampling switch), then the 3.3MΩ source doesn’t provide enough current for the pin to recover from the kick, and doing more averaging just makes things worse. With long intervals between samples (no hardware averaging), the input pin has time to recover, even with the 3.3MΩ source.
This explanation makes sense out of more of the data than just the low-frequency behavior—it also explains the further downturn in the response for 32× averaging at the high end of the sampling rates checked. At those sampling frequencies, the interval between bursts of 32 samples gets short enough that the input pin can’t recover even in the time between bursts.
The bottom line here is that the input to the ADC pins can only be modeled as a simple impedance if the source impedance is low enough that the noise stuck on the input line by the sampling is eliminated before the next sample is taken. Obviously, 3.3MΩ is much too large a source impedance for use with PteroDAQ. But how big a source impedance can I use and expect reasonable results? More experimentation is needed.
Also, I might want to add an option to PteroDAQ to allow increased sample times for higher impedance sources. The current 4-cycle sample time could be increased to 6, 8, 10, 12, 16, 18, 24, or 26 clocks (that is, up to about 3.8µs), allowing about 6–7 times higher source impedance than currently accepted, at some loss of conversion speed.