# Gas station without pumps

## 2017 September 7

### Ultrasonic transmitter and receiver impedance measurement

Filed under: Data acquisition — gasstationwithoutpumps @ 18:53
Tags: , , ,

In Ultrasonic rangefinder with Analog Discovery 2, I looked at the impedance of  an ultrasonic transmitter with the Analog Discovery 2, but I only modeled the transmitter as a capacitor, not modeling the resonances.

So today I collected new data, both for a transmitter and a receiver, using a 1nF C0G (1%) capacitor as the reference impedance, so that I could have clean data from a known pair.  I also looked at the transmitter+receiver as a network, and located the peaks of the signal transmission.  I was curious whether they corresponded more to transmitter or receiver resonances.

I could model the transmitter quite effectively as a capacitor with 4 LCR resonators in parallel.

I could model the receiver quite effectively as a capacitor with three LCR resonators in parallel.

The fitting was done with gnuplot, fitting one resonance at a time starting with the lowest frequency one, then refitting the previously fit parameters to tweak the fit. The radius of convergence for the fitting is pretty small—I needed to get the LC resonant frequency pretty close to correct before the fitting would converge. Increasing L makes the down-spike and up-spike closer together, and R controls how low the minimum gets, so I could get reasonable initial values (good enough to get convergence) without too much guessing, by plotting using the initial values, adjusting L to get the spacing between the spikes about right, adjusting C to get the resonant frequency right, and doing a rough guess that R is about the minimum value.

The peaks of the transmitter+receiver characteristic seem to correspond most closely to the minimum impedance points of the transmitter, which is reasonable when you consider that I’m driving the transmitter from a fixed voltage—the power is going to be V2/R, so power out is maximized when the impedance is lowest.  The one exception is the 331kHz peak, which seems to fall on the higher frequency of the two closely spaced transmitter resonances, and near the peak of receiver impedance. (Of course, only the 40kHz resonance of the transmitter or receiver actually gets used—the other resonances don’t provide nearly as much response in the transmitter+receiver pairing.)

Zooming in on the transmitter impedance for the high-frequency resonances, we can see that there are minor resonances that have not been modeled, but that the model does a good job of capturing the shape of the peaks. The peak of the transmitter+receiver response here falls on the higher-frequency resonance.

I did all my modeling with just the magnitudes of the signals, so it is interesting to see how well the model fits the phase response.

I got excellent matches to the phase response (even when I zoomed in on each peak), except for the low-frequency region, where the impedance seems to have a negative real part (phase < -90°).

I do have models for no resonance, single resonance, two resonances, and three resonances for the transmitter, as well as the four-resonance model. If a simplified model is needed, then it is better to take one of those fits, rather than omitting parts of the more complicated model, as each resonance affects the other parameters somewhat.
As a simple example, the receiver can be modeled as just a 739pF capacitor, but the LCR circuits contribute some of the capacitance, so 708pF gets used for the base capacitor of the model with the 3 resonances.

## 2017 August 23

### Motor testing

Filed under: Data acquisition,Robotics — gasstationwithoutpumps @ 02:20
Tags: , ,

I bought some 6V motors with mounting brackets, wheels, and Hall-effect rotary encoders from Ali Express (https://www.aliexpress.com/item/1-set-2-set-High-torque-Electric-Encoder-Gear-Motor-DC-6V-210RPM-0-13A-Mayitr/32820157282.html), which arrived today, so I spent most of the day playing with them and trying to characterize them.

The first thing to do was to try to relate voltage, current, and speed.  I used the power supply in the Analog Discovery 2 to drive the motor through a resistor, monitoring both the voltage across the motor and the current through the resistor.  I used a Teensy LC board running PteroDAQ to monitor the frequency of the pulses from one of the Hall-effect sensor.  Initially I had tried looking at the pulses with the logic analyzer of the Analog Discovery 2, which gave me a fine short trace from which I could look at individual pulse widths and periods, but not get a long-term average frequency.

Varying the voltage on the motor gave different speeds, and the speed was linear with the voltage.  The current also went up with the voltage, but not linearly (it remained around 40mA even for very low voltages, and only went up to about 67mA at the highest voltages).

The standard simplified model for a motor is an “RLV” model: a resistor, an inductor, and a speed-dependent voltage source (referred to as the back-EMF).  $V(s) = R I + L dI/dt + V_s s$, where the speed is s, and the current is I. With a constant input voltage, the inductor is not really modelable, so I came up with an RV model:

The speed here is represented by the Hall-effect sensor, which gives 11 ticks per turn of the motor shaft. The back-emf is about 7.64 mV/Hz and the resistance is about 4.8Ω.

I needed about 2.5–3V to start the motor, but once it was running I could reduce the voltage to around 0.667V before the motor stopped (the lower speeds in the plot above were done by reducing the voltage with the motor running).

I tried measuring the impedance of the motor with the new impedance tool of Waveforms 2015. I got somewhat different results depending on the frequency used and the test voltage. For ±1V and low frequencies (under 300Hz), I got around 3.5–3.6mH+4.25Ω, but at higher frequencies the inductance dropped and the resistance increased: at 40kHz I had 1.946mH+438.5Ω. With a 5V signal I got 5.1mH+4.88Ω around 20Hz and down to 1.62mH+484Ω at 40kHz. The resistances at low frequencies are fairly consistent with the resistance I inferred from the back-EMF+IR model. So I’m reasonably comfortable in modeling the motor as having
$V(s) = (7.64 mV/Hz) s + 4.8\Omega \,I + 4mH \,dI/dt$.

I may have to tweak that inductance, though, as I’m not sure which frequency’s inductance is relevant.

I also recorded the turn-on transients of the motor. I tried first doing this by turning on the power supplies while the oscilloscope was waiting for a trigger, but the power supplies turn on quite slowly, so I added an nFET to the negative rail and controlled the gate with a pushbutton. The pushbutton connected the gate to a positive voltage and the gate had a large pulldown resistor to ground. The large pulldown resistor eventually turns the FET off when the button is released, but slowly enough that contact bounce does not result in turning the nFET on and off.

The voltage initially spikes up to the supply voltage, then the current increases through the inductor, until the resistive voltage divider controls the voltage. Then the motor starts moving and the back emf increases. The initial spike is very short (about 2ms), but spinning up the motor takes over 200ms.

You can see the enormous commutator signal in the voltage and the current. The current is directly controlled by the commutation—the voltage signal is only affected because of the IR drop across the 10Ω sense resistor I used for sensing the current.

We can use the initial turn-on spike to estimate the inductance, by looking at the exponential curve for the growth of the current:

The current is growing towards 412.5mA with a time constant of 311.76µs.

The inductance is just R times the time constant, where R is the series resistance (the 10Ω sense resistor and the 4.8Ω internal resistance—I’ll ignore the on-resistance of the MOSFET). $L = 311.76 \mu s 14.8\Omega = 4.61 mH$.

All the speed measurements here were in terms of how fast the Hall-effect sensor on the motor shaft was pulsing, but how fast is the output shaft of the gearbox turning? There are two questions: what is the ratio of sensor pulses to motor rotations, and what is the ratio of motor rotations to output shaft rotations?

The website for the motor claimed “Encoder motor end: 11 signals”, which I took to mean that there were 11 pulses per rotation.  I confirmed this by doing a Fourier transform of the commutation signal (the current) and of the pulse signal.  The fundamental of the pulse corresponded to the 11th harmonic of the current, so there were 11 pulses per turn of the motor shaft.

Determining the gear ratio (ratio of motor speed to output shaft speed) was more difficult.  I set up an optical interrupter to be blocked by a bit of electrical tape on the end of the output shaft once per revolution, and recorded the optical signal on every rising edge of the Hall-effect pulse using PteroDAQ.  By recording for a while, I could count the number of Hall-effect pulses for some integer number of shaft rotations.  Taking the pulses/output rotation and dividing by 11 gave me the motor-shaft rotations per output shaft rotation (the gear ratio I was seeking).  Getting a real number for this was fairly straightforward, but I wanted a rational number using products of small integers, corresponding to the gear teeth on the gears!

For one run, I had 856 shaft rotations with 200523 or 200524 pulses (depending whether I counted between rising edges or falling edges of the optical signal), giving me 234.255841121 to 234.257009346 pulses per rotation, or a gear ratio of 21.2959855565 to 21.2960917587.

I did a longer run with 4811 shaft rotations with 1126978 pulses or 1127000 pulses , giving me 234.250259821 to 234.254832675 pulses per rotation or a gear ratio of 21.2954781655 to 21.2958938795.

I converted the gear ratio to a continued fraction using my pocket calculator, getting

$21+\frac{1}{3+\frac{1}{3+\frac{1}{-3+\frac{1}{2+\cdots}}}}$,

which expands to

21 + 1/3 = 21.3333333…

21 + 3/10 =21.3

21 + 8/27 = 21.29630…

21 + 37/125 = 21.296  = 2662/125 = 2 * 11^3 / 5^3

The last ratio factors nicely, and looks feasible for a gear ratio.  To confirm my estimate, I carefully took apart one of the gearboxes and counted the teeth on the gears.  I got

• motor shaft 12T
• engages 22T linked to 10T
• engages 22T linked to 10T
• engages 22T linked to 10T
• engages 24T on output shaft

This gearing does indeed give me the 2 (11/5)^3 gearing I calculated!

So my gear ratio is exactly 21.296 and I have exactly 234.256 pulses per rotation of the output shaft (with the quadrature coding from two Hall effect sensors, I get exactly 937.024 transitions per rotation).

With 6.0364V across the motor, I got 752.37Hz from the sensor, so the output shaft was rotating at 3.212Hz, or 192.7 rpm (somewhat slower than the claimed 210 rpm for 6V no load). The wheels that came with the motors have a circumference of 215mm, so the maximum speed would be 69cm/s, which is about 1.54 mph—not a real zippy machine, but more than fast enough for a small robot.

The tires are pretty squishy, though, and if I want to use the wheel turns to keep track of location, I’ll probably want wheels whose diameter doesn’t vary with the load—perhaps I could wrap the hubs with friction tape. The hub circumference is only 161mm. I could also laser-cut some wheels to get whatever diameter I want.

## 2017 August 15

### Beacon detector SPI interface

Filed under: Robotics,Uncategorized — gasstationwithoutpumps @ 12:53
Tags: , , ,

In Beacon detector board, I introduced the hardware for the IR beacon detector, and in Digital tone detection with Goertzel’s algorithm, I discussed the algorithm used for detecting a 2kHz signal in a noisy background.  In this post I’ll talk about the software for interfacing the board to microcontrollers as if it were a standard peripheral device.

When I was designing the hardware, I had to choose between providing a UART interface, an SPI interface, or an I2C interface. At one point, I considered including all three, since I had just enough pins to do that and plenty of board space for connectors.

My son urged me to use a UART interface, since asynchronous communication is much easier work with than the two synchronous interfaces—there are no tight timing constraints. UART communications tends to be slow (115200 baud is a common top speed, resulting in a maximum of about 11.5–12.8kbytes/second transferred), and the two sides must agree on the baud rate to within 2.5%. But there are no latency constraints—you can respond to a request whenever you are finally ready—so there are no worries if you need to wait for a timer task to complete before communicating. The main downside of a UART interface (besides the usually low speed) is that it is a one-to-one interface. Two pins are needed for each UART a microcontroller uses, while the synchronous interfaces provide shared bus communication.

I knew that I could do a UART interface and for the small amounts of data I needed to communicate (10–75 bytes every 60th of a second, or 600–4500 bytes/s) it would be fast enough. But I wanted a challenge that would help me learn something new, so I decided to do a synchronous interface. Of the two choices supported by the Teensy LC hardware, SPI and I2C, the SPI interface looked the simpler to implement in software, as the timing seemed a little less challenging, and there was a FIFO that could be loaded with several bytes of information to transfer, reducing the timing demands. (In retrospect, I2C may have been easier—I’ve not tried it, though, so there may be some unexpected challenges.)

I created the board with only one I/O port (other than the USB port used for programming the board), the SPI0 4-wire interface using pins CS=D10=PTC4, MOSI=D11=PTC6, MISO=D12=PTC7, SCK=D13=PTC5.  I used a 6-pin right-angle header at the edge of the board, so that I would be able to use a ribbon connector to connect to another microcontroller. The order of the pins is the same as Digilent uses for their PMOD connector—an arbitrary choice, but there does not seem to be a commonly accepted standard for SPI connections.

The choice of pins was the first mistake I made in the SPI design—I should have used SPI1 instead of SPI0.  In reading the reference manual for the KL26 chip that is the basis for the Teensy LC, the SPI FIFO is only implemented for SPI1, and not for SPI0.  Also, the legal SPI clock speeds are different for the two interfaces:  SPI0 is clocked off the bus clock (default 24MHz on the Teensy LC) and SPI1 off the system clock (default 48MHz). The external clock SCK is allowed to go from 0Hz to ¼ the module clock, so 6MHz for SPI0 and 12MHz for SPI1.

The lack of a FIFO on SPI0 made the timing for loading the transmit buffer a little tricky.  The hardware has two registers for the transmit: the shift register used for serializing a byte and the transmit buffer that holds the next byte to transfer to the serial register.  If the transmit buffer is not loaded in time for the serial shifting, then the SPI interface will duplicate the previous byte, messing up communication.

The Teensyduino library contains SPI master software, but not SPI slave software.  I was wondering about the reason for that before I started my coding, but I quickly realized why—the timing for SPI is almost entirely under control of the master and the slave is constrained to respond at times specified by the master.  The most common SPI protocols for peripherals consist of the master sending a 1-byte (or longer) command to the slave and getting a response back in the next byte slot(s).  This gives the slave about half a clock period to interpret the command and prepare the response. With a 1MHz SCK, that gives the processor about 500ns to set up the response. That’s plenty of time for an all-hardware system, but is a very tight constraint for a software implementation.  In fact, given that the interrupt latency on the KL26 can be about 800ns, it is an impossible constraint—I don’t even know that I need to send a byte, much less figure out what it is, in the available time.  The more complicated I2C interface allows a slave to stretch out the clock when it can’t respond in time, but the SPI interface doesn’t allow the slave to change the clock rate.

So I couldn’t use the most common SPI interface protocol of command followed by immediate response. I had a few choices of workarounds for the latency problem:

• Have a standardized packet of material that is sent independent of what the master does.  This seems to be the solution used by SPI slave libraries others have written for the Teensy boards (not part of the standard Teensyduino library).  It allows high throughput, especially if DMA is used to load the transmit information, but is not very flexible.  It is not a commonly used protocol on SPI peripherals.
• Require the master to wait before asking for the response bytes.  This is very flexible and allows the SPI bus to run at maximum speed during transfers, but is not really in the spirit of a synchronous interface—the slave should respond at a standardized time, and the master should not have to know how long it will take the slave to be ready to send.
• Send a dummy byte in the slot after the request so that I have a full byte time (8 SCK periods) instead of half a bit time to get the right information ready. A disadvantage is that the throughput is reduced—the dummy bytes take up bus time without communicating useful information. If the protocol calls for a 1-byte command and a 1-byte response, then each transfer would take 3 byte times.  (A 1-byte command and an n-byte response takes n+2 byte times.)

I ended up using a slight variant of the dummy-byte approach: I allow the master to send new commands before the first response comes back.  Dummy bytes are only added when there are no real bytes to send, so a series of n commands requesting 1-byte responses could be sent in a row, with the total time for the transfer taking n+2 byte times—the first two slots of which the slave is sending dummy bytes, and the next n are the requested data.

To make this protocol work, I had to ensure that the SPI interrupt priority is higher than any other interrupts in the program, in particular, higher than the PIT timer that I was using for the 15kHz sampling frequency.  This means that the SPI transmissions will introduce jitter into the ADC sampling—I’ve not yet determined how much of a problem this will be, but I suspect it won’t be much of a problem, since it will only affect one or two samples in the 250-sample filter block.  The default interrupt priority on the KL26 processor in the Teensy LC is for all interrupts to be at the highest priority, so I had to lower the PIT priority rather than raising the SPI priority.

The basic notion is that I keep the SPI transmit buffer always full.  When there is a transmit-buffer-empty interrupt, I load the buffer from a software FIFO I maintain, or with a dummy byte (0xff) if there is nothing in the FIFO.  The responses to a command are loaded into the FIFO.  As long as the SPI interrupt response (including interpreting the command and any FIFO loading or popping) takes less than the time of one byte, the protocol runs smoothly.  With commands that can send up to 4-byte responses, I was able to run SCK up 1.25MHz without losing synchronization.

My current, minimal command set for the beacon detector has the following commands:

1. Freeze the information from filter so that all subsequent commands refer to the same set of data.  Return 1 on success, 0 on failure.  (The failure is only possible if the request is sent too soon after a reset of the beacon detector board.)
2. Report which channel has the highest power (1-byte: 0xff if no beacon detected, otherwise 0..7)
3. Report the estimated angle of the beacon in 0.1° units (2-bytes: 0..3599)
4. Report the power in the max-power channel (4-bytes: unsigned int)

I could also report the power in specific channels and the power from an alternative (3kHz instead of 2kHz) filter for each channel, which would be another 64 bytes of information, but I’ve not implemented those commands yet.  The minimal set I currently have responds with 8 bytes of information, so takes 10 byte times for a burst of communication. With the highest clock rate I’ve gotten to work (SCK=1.25MHz), a full packet takes 64µs, which would interfere with only one or two samples of the 15kHz sampling.

I may play around with different command sets after I get another board programmed as a master to communicate with the beacon detector and determine what information I really need from the beacon detector.  One possibility is to use just a single 2-byte response that encodes everything but the power: that would allow a 4-byte-time packet (25.6 µs).

Setting up the SPI software ran into all the usual problems with setting up a peripheral on a Kinetis ARM processor—there are many registers that need to be set up correctly, and nothing works until they are all right:

• Turn on the SPI module clock: SIM_SCGC4 |= SIM_SCGC4_SPI0
• Set the SPI control registers SPI0_C1 and SPI0_C2 for 4-wire SPI with CPOL=1, CPHA=1, 8-bit mode, interrupt on receiving a byte or on transmit buffer empty.
• Set up the isr to interpret the recieved bytes and keep the transmit buffer full.
• Configure the 4 pins used to be ALT 2 (SPI0) rather than the default GPIO.
• Set the priorities using NVIC_SET_PRIORITY(IRQ_SPI0, 0) and NVIC_SET_PRIORITY(IRQ_PIT_CH1, 64).  The KL26 processors have only 4 interrupt priority levels that are multiples of 64.  Lower numbers are higher priority.
• Enable the interrupts with NVIC_ENABLE_IRQ(IRQ_SPI0)

I debugged the SPI interface using the protocol and logic analyzer tools in the Analog Discovery 2.  I found the user documentation for these tools really awful (almost no information), but I managed to get things working by trial and error (except for the “sensor” script options for the SPI protocol tool—that always resulted in the spinning beachball and force-quitting Waveforms 2015).  I initially tested with the “Master” tab of the protocol tool, but I fairly quickly switched to using the “Custom” tool which allowed me to set up more complicated sequences of reads and writes, though eventually I simplified back to writes that could be done with the “Master” tab.

The “debug” mode of the protocol tool sets up the logic analyzer to see the signals, but then doesn’t provide the decoding of the protocol in the protocol tool—one has to go to the logic analyzer to set up the triggering, switch to the protocol tool to send the stimulus, then switch back to the logic analyzer to see the results.  It is possible to get the protocol tool and the logic analyzer tool in different windows (double-click on the tab for the tool you want in a new window), but my screen is too small for showing both windows in sufficient resolution at once.

To see when the interrupt service routine for the SPI was active I added CORE_PIN1_PORTSET = CORE_PIN1_BITMASK to the beginning of the isr and CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK, and used some wirewrap wire to get the pin 1 signal out to the logic analyzer. I’d not added test points for the unused pins, but because the Teensy board is socketed with female headers, it was easy to wrap a wire around the pin before pushing the board into the female headers, and use a loose header pin to connect the other end of the wire to DIO6 of the logic analyzer.

Here is a result of a test of sending the 4 commands in a row in an 11-byte frame, to make sure that the dummy bytes occur in the right places (in the first 2 and last slots of the 11-byte frame):

The MISO line shows the correct responses from the beacon detector: 0xff, 0xff, 1 (freeze ok), 0 (channel 0), 0x00e1=225=22.5°, power=0x08436020=138633248.

As it turns out, the end of the isr for the 4-byte response comes 0.4µs later than it should if there had not been any other bytes already in the queue. Indeed, if I start with the “4” command, things just barely work, because the isr routine starts a little sooner. The 6.8µs delay to the end of the isr routine suggests to me that the maximum safe rate for SCK is only about 1.15MHz, not 1.25MHz.  I’ll have to do a lot of testing with many data packets, to see what rate is really safe without intermittent errors.  That will have to wait until I’ve written a program to act as the master (unless I can figure out why the “sensor” script keeps crashing Waveforms 2015).

## 2017 July 13

### Analog Discovery 2 oscilloscope input impedance fixed

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 23:25
Tags: , ,

This morning in Analog Discovery 2 oscilloscope input impedance, I wrote

I cannot fit a model based on the input divider circuit to the data—I keep getting a negative capacitance for C9 or C8, so that they can cancel each other.  These models also make C1 around 50pF.

So I can reconcile the DC behavior (1.044MΩ is well within the ±2% measurement error of the nominal 1.04MΩ), but not the AC behavior of the scope inputs.

I must be missing something, but what?  Any useful suggestions (which don’t involve modifying the Analog Discovery 2) are welcome.

This evening I figured out what I was missing. The model I was trying to fit was the following one for the oscilloscope, with a 2MΩ resistor in series as the reference impedance:

There is a natural, internal split into an 820kΩ and 220kΩ resistance in the input voltage divider (component numbers here are for channel 1, but channel 2 is identically designed).

What I was missing was parasitic capacitance from the breadboard and scope wiring. If I model a capacitor (Cref) in parallel with the 2MΩ resistor and another capacitor (Cextra) in parallel with the scope, I can get a good fit.  I can leave all the internal resistors and capacitors at their nominal values, and fit for several different values for the trim capacitor C8:

I can get an excellent fit with Rref being only a little over 1% off and reasonable parasitic capacitance values.

### Analog Discovery 2 oscilloscope input impedance

Filed under: Circuits course,Data acquisition — gasstationwithoutpumps @ 11:43
Tags: ,

I have been blindly trusting the documentation for the Analog Discovery 2 that claims that the input impedance of the differential oscilloscope channels is 1MΩ || 24pF.  Yesterday, when my son was measuring the input impedance of the reference inputs of a sigma-delta ADC, we had reason for a while to doubt that claim, so I measured the input impedance in a simple way:  I put a 2MΩ 1% resistor in series with one input channel and used the other input channel to measure the voltage across the series pair. I swept the network analyzer from 10Hz to 1MHz, and recorded the voltage gain (and the phase).  The voltage gain is not well-fit by a simple (1MΩ || 24 pF) model, as the impedance does not keep decreasing.  It seems to be well modeled by a model with Rs+(Cp||Rp), though.

The reported voltage gain for Channel 2/Channel 1 is well fit by a voltage divider.

Because the Analog Discovery 2 reports gain for Channel 2/Channel 1, I had to invert the data to get it in the form I wanted for my model (I could, alternatively, have swapped the legs of the voltage divider in the model).

The phases were also well fit by the models, though I did not use the phase information in the fitting. (I tried refitting using just the phase information, but that did not change the parameters by much, nor did it visibly improve the fit of the measured phases, so I left the parameters with just the amplitude fit.)

The DC impedances are both 1.044MΩ, very close to the specified value, but the capacitor is over twice the specified value, and not directly in parallel with the resistance.  The reference resistor I used is supposed to be a 2MΩ±1% resistor, but it was part of a cheap assortment, and we’ve found these cheap assortments to often be slightly out of spec, so I’d not trust it to be better than ±2%.

The 200kΩ/800kΩ split is not very surprising, when we look at the circuit for the input divider of the oscilloscope (from the hardware reference manual):

There is a natural, internal split into an 820kΩ and 220kΩ resistance in the input voltage divider (component numbers here are for channel 1, but channel 2 is identically designed).

The appearance of the 200kΩ/800kΩ split in the model for the input impedance suggests that the trimmer capacitor C8 is not properly adjusted.  If all capacitance and resistance values were nominal, then C8 should be set to 39.59pF, to provide a flat response from the voltage divider (at the high-gain setting), producing an input impedance of (1.04MΩ || 26pF).  But C8 only has a 5–20pF range, so perhaps there are some other, parasitic capacitances that change the desired trimming.

I cannot fit a model based on the input divider circuit to the data—I keep getting a negative capacitance for C9 or C8, so that they can cancel each other.  These models also make C1 around 50pF.

So I can reconcile the DC behavior (1.044MΩ is well within the ±2% measurement error of the nominal 1.04MΩ), but not the AC behavior of the scope inputs.

I must be missing something, but what?  Any useful suggestions (which don’t involve modifying the Analog Discovery 2) are welcome.

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