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2016 December 27

FET I-vs-V with Analog Discovery 2 again

 

In FET I-vs-V with Analog Discovery 2, I plotted Id vs. Vgs curves for an nFET:

The Ids-vs-Vgs curves do not superimpose as nicely as curves I’ve measured with PteroDAQ. I don’t yet understand why not.

Yesterday, I played with sweeping the power supply (Power waveform generator).  In this post, I used that capability to plot Id vs Vds curves for different gate voltages (Vgs) of a different nFET (since the AOI518 is an obsolete part).  The setup is the same as for the previous test—the function generator is connected to the gate, the power supply to the drain load resistor in series with the nFET whose source is connected to ground, and the two oscilloscope channels monitor the voltage across the load resistor and across the nFET.  The difference is that I use the power-waveform option to put a 1Hz triangle wave on the power supply, but put just a DC offset (AC amplitude 0V) on the function generator output, so that the gate voltage is constant as the drain voltage is adjusted.

The saturation regions are well plotted up to Vgs=2.7V. I averaged 10 or 20 scans for each of these curves, to reduce quantization noise for small voltages or small currents.

The saturation regions are well plotted up to Vgs=2.7V. I averaged 10 or 20 scans for each of these curves, to reduce quantization noise for small voltages or small currents.

I got quite different results when I removed and replaced the nFET from the breadboard—the breadboard contacts seem to have a variation of about ±0.05Ω in resistance, which is much larger than the on-resistance of the nFET when fully on. I took measurements with a wire between the source and drain to estimate the wiring resistance, but wiggling the wire produced very different results.

In the next graph, I tried subtracting off the wiring resistance to get the on-resistance, but I’m really quite dubious about the measurements smaller than 0.5Ω, because of the unrepeatability of the bread board contact resistance.

The numbers here look good (close to the spec sheet), but repeating the measurements could result in ±0.1Ω, which makes the Ron measurements for fully on transistors rather useless.

The numbers here look good (close to the spec sheet), but repeating the measurements could result in ±0.1Ω, which makes the Ron measurements for fully on transistors rather useless.

By using a smaller power resistor, I could probably get saturation currents for slightly higher gate voltages, up to the current limit of the power supplies in the Analog Discovery 2, but better on-resistance measurements would require a better jig for making low-resistance contacts to the FET.

By using a much larger resistor, I could measure low currents more accurately, which would give me a better idea of the leakage currents—I don’t really believe the measurements for Vgs=2.1V, because the current appears to decrease with increasing Vds, which is probably an artifact of measuring a small difference in voltage with a large common-mode signal.

I tried using larger resistors to measure the saturation currents, but the results varied a lot depending on what size load resistor is used. I believe that the difference is due to temperature changes from self-heating. If I sweep out to larger Vds voltages (using a smaller load resistor, hence smaller IR drop across it), but about the same saturation current, I’m dissipating more power in the transistor, so making it warmer. This appears to increase the saturation current. Reducing the range of the voltage with the same load resistor drops the curve down, just as increasing the load resistor does. I suspect that proper measurement requires a jig that holds the transistor at a nearly constant temperature, as well has having very low contact resistance.

The saturation current seems to vary by about ±10% as I change load resistors. The effect is most likely thermal—note that using a smaller voltage sweep for Vgs=2.3V and Rload=51Ω resulted in almost the same curve as Rload=270Ω, because the power dissipated was about the same.

The saturation current seems to vary by about ±10% as I change load resistors. The effect is most likely thermal—note that using a smaller voltage sweep for Vgs=2.3V and Rload=51Ω resulted in almost the same curve as Rload=270Ω, because the power dissipated was about the same.

Note that the thermal explanation also works for explaining why the superposition does not work well for the Id vs Vgs plots—at lower load resistances, more power is dissipated in the transistor, and it gets warmer, shifting the current curve upward.

2016 December 26

Power waveform generator

Filed under: Data acquisition — gasstationwithoutpumps @ 21:53
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I was playing around a little more today with my Analog Discovery 2 USB oscilloscope, and found that one could set up the power supplies to be high-power waveform generators by setting configuration 6 in the device manager.  The power supplies are not great function generators, of course, as they are switching power supplies, but I can see some use cases for this functionality.

The power supplies are nominally limited to 700mA, so I wondered whether they had the same sort of sharp clipping that the function generator has (see FET I-vs-V with Analog Discovery 2).  I tested the power waveform generator with several different loads:

With no load, the power supply waveform generator has trouble with small voltages (no resistance to drain the capacitance) and has fairly high noise, but is nicely linear. At high load (1.8Ω) the voltage is substantially less than specified.

With no load, the power supply waveform generator has trouble with small voltages (no resistance to drain the capacitance) and has fairly high noise, but is nicely linear. At high load (1.8Ω) the voltage is substantially less than specified.

We can get a clearer idea of the behavior by looking at the difference between the power waveform generator and the normal waveform generator:

At low voltages, the regulator's output capacitor is not discharged fast enough without a load resistor. The regulator also does a better job of keeping the noise down with higher load.

At low voltages, the regulator’s output capacitor is not discharged fast enough without a load resistor. The regulator also does a better job of keeping the noise down with higher load.

With no load, the noise on the power waveforms is about ±4mV, but at high load, it drops to about ±1mV.

The noise is periodic with a frequency of about 1.024kHz, which is much too low a frequency for a switching regulator—it is actually from the sampling frequency for the waveform generator generating a 1Hz triangle wave (210 samples in wavetable). The usual waveform generator has four times as high a sampling frequency, so the error is mostly just quantization error from the power waveform generator, though a single step from the power waveform generator takes about 250µs to settle, so the 1Hz maximum frequency for the power waveform channels seems reasonable. With a 10Ω load, the settling time is reduced to about 50µs and the noise on each step is about 500µV RMS (not counting the quantization error).

With the 1.8Ω load, I let the current get as high as 927mA (well above the 700mA specification), and there is no sign of clipping. We can more reasonably model the power waveform generator as having an internal resistance. For the 1.8Ω and 10Ω loads, I plotted the equivalent internal resistance as a function of voltage (for the larger voltages):

The internal resistance is approximately 100mΩ—180mΩ, with the larger values at higher voltages. There is a clear anomaly at half the full-scale voltage (2.5V for 10Ω and 0.9V for 1.8Ω).

The internal resistance is approximately 100mΩ—180mΩ, with the larger values at higher voltages. There is a clear anomaly at half the full-scale voltage (2.5V for 10Ω and 0.9V for 1.8Ω).

I believe that the power waveforms will be useful for characterizing transistors, especially for sweeping a range of Vds voltages that require a substantial current.

2016 December 15

Function generator bandwidth of Analog Discovery 2

Filed under: Data acquisition — gasstationwithoutpumps @ 15:56
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The network analyzer function of the Analog Discovery 2 USB oscilloscope makes it easy to characterize the function generator’s bandwidth—just connect the function generator to the input channel (making sure that the input channel is not specified as a reference) and do a sweep.  The only choice is whether to use the wires that come with the basic unit or the optional BNC adapter board and scope probes.  I tried it both ways (and with both 1X and 10X settings of the scope probes), using 1V amplitude on the waveform generator one in all cases:

There is not much difference in the bandwidth between 10X probes and wires (both high impedance) (8.5–8.8MHz bandwidth), but the 1X scope probes provide higher bandwidth—higher than the 10MHz measurable with the network analyzer.

There is not much difference in the bandwidth between 10X probes and wires (both high impedance) (8.5–8.8MHz bandwidth), but the 1X scope probes provide higher bandwidth—higher than the 10MHz measurable with the network analyzer.

I tried loading the function generator with resistors, but this made essentially no difference in the frequency characteristics. It isn’t the 1MΩ resistance of the scope that matters, but the capacitance of the oscilloscope plus probe.

So I tried adding capacitive loads and found that I got a very clear LC resonance. With a 330pF load, I got the peak near 10MHz to approximately cancel the drop:

The resonance around 9.1MHz with a 330pF load is actually a little too strong and over-corrects for the drop in bandwidth. Adding 6.8Ω in series with the 330pF capacitor makes a load that nicely compensates for the inductance of the wires.

A resonance around 9.1MHz with a 330pF capacitor implies an inductance of about 0.93µH, which is in a reasonable ballpark of the sort of inductance one would expect for 80cm of wire (4 wires each about 20cm).

2016 December 12

FET I-vs-V with Analog Discovery 2

Filed under: Data acquisition — gasstationwithoutpumps @ 17:41
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Yesterday, in FET Miller plateau with Analog Discovery 2, I started posting about the Analog Discovery 2 USB oscilloscope, an oscilloscope with two differential input channels, 2 arbitrary-waveform function generators, a dual regulated power supply, and a logic analyzer.

I want to modify something I said yesterday:

If I look at the square wave with nothing but the scope attached, then I see a voltage of about 4.005V.  With a 100Ω load, I see 3.44V, which gives an output impedance of 16.4Ω.

I think that what I was seeing should not really be characterized as an output impedance, but as a current limitation.  The AD8067 op-amp that is the output device for the waveform generator is specified to have a 30mA current limitation (for -60dB spurious-free dynamic range) and 105mA short-circuit current, and 3.44V/100Ω is 34.4mA.  I can test this assumption by seeing what happens with a triangle-wave signal:

The triangle wave with a 100Ω load is clipped at approximately ±3.48V, corresponding to a current limitation of ±34.8mA.

The triangle wave with a 100Ω load is clipped at approximately ±3.48V, corresponding to a current limitation of ±34.8mA.

With 100Ω, I get ±3.48V, for ±34.8mA.  With 33Ω, I get ±1.475V, for ±44.7mA.  With 18Ω, I get +1.014V, -0.8458V, for +56.3mA, -47mA.  In each case, I am getting clear clipping, not scaling of the signal, so the best model is as a 0Ω output impedance, combined with current limitation, rather than as a non-zero output impedance.  The current limitation is not quite constant—I can get more current at lower voltages.

Something else you can see in the image above is that the time axis is not limited to starting at 0—I can move the trigger point around either graphically or by typing into boxes that hold the trigger level and time position for the line in the middle of the screen.

What I really wanted to show today was not the waveform generator current limit, but Ids-vs-Vgs plots for an nFET (the same old AOI518 nFET that I was playing with yesterday). I can use the differential inputs to measure the gate-to-source voltage on one channel and voltage across a drain resistor on the second channel.  It is easy to adjust the voltage range for a slow triangle wave driving the gate, and to look at an XY plot:

Voltage across 20Ω drain resistor to 5V for AOI518 nFET for a range of gate-to-source voltages. To get the large current, an external 5V wall-wart had to be connected.

Voltage across 20Ω drain resistor to 5V for AOI518 nFET for a range of gate-to-source voltages. To get the large current, an external 5V wall-wart had to be connected.

It would be nice if there were a way to scale the voltages across the load resistor to plot currents on the XY plot, instead of just voltages.  I can, of course, do this scaling with external programs, as I have with other measurement devices. I tried changing the resistors to get different current ranges, exporting the data in tab-delimited formats, and plotting superimposed I-vs-V plots. The results were not as good as I’ve gotten in the past using PteroDAQ:

The Ids-vs-Vgs curves do not superimpose as nicely as curves I’ve measured with PteroDAQ. I don’t yet understand why not.

I’m also not sure why there seems to be a 4µA leakage current.  At the top end, I’m not hitting the current limit of the voltage regulator, which is 700mA when powered by an external power supply, as I did here.

2016 December 11

FET Miller plateau with Analog Discovery 2

Filed under: Data acquisition — gasstationwithoutpumps @ 21:49
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I recently bought myself a birthday present: an Analog Discovery 2 USB oscilloscope. The device normally costs $279, but  I qualify for the academic discount, which brought the price down to $179—a very good deal.  This oscilloscope is better in every way than the Bitscope BS10 that I bought about 4 years ago: functions, resolution, bandwidth, software, … . The Analog Discovery 2 is also cheaper (at least with the academic discount).

I’ve been playing with it a little bit, and I decided to try to reproduce a few of the plots that I have done before.  This post is about creating the plot of the Miller plateau for an nFET (see, for example, More on nFET Miller plateau).  With the Bitscope, I had to filter the 5V power (which was just passed through the device, record many traces, process them with a program I wrote myself to remove the jitter in the triggering, average them, and plot with gnuplot).

With the Analog Discovery 2, I set the built-in power supply to 4V, set the function generator to a 1kHz square wave from 0V to 4V, and put the scope leads to measure Vgs and Vds for the following circuit:

The 100Ω gate resistor is to limit the current from the 1kHz square wave generator, so that the Miller plateau is stretched out in time.

This setup produced a very nice plot without any averaging—the Waveforms 2015 software that comes with the Analog Discovery 2 does the interpolation between samples to dejitter the waveform:

With a 100Ω gate resistance, the plateau is about 146ns long (easily measured with a pair of cursors not shown in this image).

With a 100Ω gate resistance, the plateau is about 146ns long (easily measured with a pair of cursors not shown in this image).

The average voltage is about 2.87V, so the current is (4V-2.87V)/100Ω=11.3mA, and the gate drain charge is 1.65nC, about half the 3.2nC on the data sheet (which was measured with different circuit parameters and is supposed to be a worst-case).  Note that this is a single trace, but multiple traces show almost no jitter, even though we are sampling at the full  100 Msample/second rate.  Averaging the traces would not make much difference in the signal.

If I replace the 100Ω gate resistor with a wire, I get a shorter Miller plateau:

With no gate resistor, the Miller plateau is only about 40.2ns long and averages 2.987V.

With no gate resistor, the Miller plateau is only about 40.2ns long and averages 2.987V.

If we assume 1.65nC in 40.2ns, we get a 41mA current, and (4V-2.987V)/41mA=24.7Ω for the output impedance of the function generator.  I may not have placed the cursors in exactly the same places on both curves, so this is a terrible way to estimate the output impedance of the function generator.

If I look at the square wave with nothing but the scope attached, then I see a voltage of about 4.005V.  With a 100Ω load, I see 3.44V, which gives an output impedance of 16.4Ω.

Of course, the square waves are not completely square, which may affect the Miller plateau measurement at high speed, but the edges are pretty sharp:

The falling edge takes about 50ns.

The falling edge takes about 50ns.

The rising edge takes about 50ns.

The rising edge takes about 50ns.

The edges are limited by the wiring, and I may be able to get better edges by using the BNC adapter board and 50Ω coax cable, rather than the wires provided, but I don’t happen to have any BNC coax cable handy.

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