Gas station without pumps

2017 January 2

LM2903 open-collector comparator characterization

Filed under: Circuits course — gasstationwithoutpumps @ 18:02
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In Last power-amp lecture, I posted an I-vs-V plot for the LM2903 comparator’s open-collector output, which I had made sometime in 2013, I think:

There are two regions of operation for the open-collector output of the LM2903. In the saturation region, the current goes up slowly with voltage (as about V^0.15, while in the "linear" region, it goes up as about V^1.5). The transition occurs when VOL is about 0.25 V, so we are almost always in the saturation region.

There are two regions of operation for the open-collector output of the LM2903. In the saturation region, the current goes up slowly with voltage (as about V^0.15, while in the “linear” region, it goes up as about V^1.5). The transition occurs when VOL is about 0.25 V, so we are almost always in the saturation region.

I decided to redo the plot using the Analog Discovery~2, as I now include the open-collector curve in the textbook (in an optional section, since we no longer use open-collector comparators). I used a 12V wall-wart and both the function generator and oscilloscope functions. I used the “custom channel” and XY plot features to get the I-vs-V plot on the screen (though I saved the data and replotted with gnuplot, to superimpose different runs). I also averaged 10 sweeps to reduce noise.

R1 was 56Ω for testing high voltages and currents, and R1 was 2.2kΩ for testing low voltages and low currents.

R1 was 56Ω for testing high voltages and currents, and R1 was 2.2kΩ for testing low voltages and low currents.

The triangle-wave generator and the nFET makes a variable load for the comparator, from slightly more than R1 up to about 1MΩ.

Even up to 11V, the LM2903 collector stays below the 20mA maximum current, but I'd want to make sure that there was some current-limiting resistor for any power-supply voltage above 12V.

Even up to 11V, the LM2903 collector stays below the 20mA maximum current, but I’d want to make sure that there was some current-limiting resistor for any power-supply voltage above 12V.

The results with the Analog Discovery 2 are much cleaner than my old results, which were most likely done with an Arduino, which has a very low resolution ADC.

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2016 December 27

FET I-vs-V with Analog Discovery 2 again

 

In FET I-vs-V with Analog Discovery 2, I plotted Id vs. Vgs curves for an nFET:

The Ids-vs-Vgs curves do not superimpose as nicely as curves I’ve measured with PteroDAQ. I don’t yet understand why not.

Yesterday, I played with sweeping the power supply (Power waveform generator).  In this post, I used that capability to plot Id vs Vds curves for different gate voltages (Vgs) of a different nFET (since the AOI518 is an obsolete part).  The setup is the same as for the previous test—the function generator is connected to the gate, the power supply to the drain load resistor in series with the nFET whose source is connected to ground, and the two oscilloscope channels monitor the voltage across the load resistor and across the nFET.  The difference is that I use the power-waveform option to put a 1Hz triangle wave on the power supply, but put just a DC offset (AC amplitude 0V) on the function generator output, so that the gate voltage is constant as the drain voltage is adjusted.

The saturation regions are well plotted up to Vgs=2.7V. I averaged 10 or 20 scans for each of these curves, to reduce quantization noise for small voltages or small currents.

The saturation regions are well plotted up to Vgs=2.7V. I averaged 10 or 20 scans for each of these curves, to reduce quantization noise for small voltages or small currents.

I got quite different results when I removed and replaced the nFET from the breadboard—the breadboard contacts seem to have a variation of about ±0.05Ω in resistance, which is much larger than the on-resistance of the nFET when fully on. I took measurements with a wire between the source and drain to estimate the wiring resistance, but wiggling the wire produced very different results.

In the next graph, I tried subtracting off the wiring resistance to get the on-resistance, but I’m really quite dubious about the measurements smaller than 0.5Ω, because of the unrepeatability of the bread board contact resistance.

The numbers here look good (close to the spec sheet), but repeating the measurements could result in ±0.1Ω, which makes the Ron measurements for fully on transistors rather useless.

The numbers here look good (close to the spec sheet), but repeating the measurements could result in ±0.1Ω, which makes the Ron measurements for fully on transistors rather useless.

By using a smaller power resistor, I could probably get saturation currents for slightly higher gate voltages, up to the current limit of the power supplies in the Analog Discovery 2, but better on-resistance measurements would require a better jig for making low-resistance contacts to the FET.

By using a much larger resistor, I could measure low currents more accurately, which would give me a better idea of the leakage currents—I don’t really believe the measurements for Vgs=2.1V, because the current appears to decrease with increasing Vds, which is probably an artifact of measuring a small difference in voltage with a large common-mode signal.

I tried using larger resistors to measure the saturation currents, but the results varied a lot depending on what size load resistor is used. I believe that the difference is due to temperature changes from self-heating. If I sweep out to larger Vds voltages (using a smaller load resistor, hence smaller IR drop across it), but about the same saturation current, I’m dissipating more power in the transistor, so making it warmer. This appears to increase the saturation current. Reducing the range of the voltage with the same load resistor drops the curve down, just as increasing the load resistor does. I suspect that proper measurement requires a jig that holds the transistor at a nearly constant temperature, as well has having very low contact resistance.

The saturation current seems to vary by about ±10% as I change load resistors. The effect is most likely thermal—note that using a smaller voltage sweep for Vgs=2.3V and Rload=51Ω resulted in almost the same curve as Rload=270Ω, because the power dissipated was about the same.

The saturation current seems to vary by about ±10% as I change load resistors. The effect is most likely thermal—note that using a smaller voltage sweep for Vgs=2.3V and Rload=51Ω resulted in almost the same curve as Rload=270Ω, because the power dissipated was about the same.

Note that the thermal explanation also works for explaining why the superposition does not work well for the Id vs Vgs plots—at lower load resistances, more power is dissipated in the transistor, and it gets warmer, shifting the current curve upward.

2016 December 15

Electret mic DC characterization with Analog Discovery 2

I tried one of the standard labs for the course, producing an I-vs-V plot for an electret microphone, using the Analog Discovery 2 function generator and oscilloscope, rather than a bench function generator and a Teensy board with PteroDAQ.

It was fairly easy to set up a 0–5V triangle wave, running at a very low frequency (50mHz, for a 20-second period).  The maximum output from the waveform generator is 5V, so setting the amplitude higher did not get larger voltages.  The signal was applied across the microphone in series with a sense resistor, and the voltage measured across the mic and across the sense resistor.

I ended up using two different sense resistors: one for measuring the current at high voltages, and one for measuring the current at low voltages, and I had to adjust the voltage scales on the two channels of the scope for the different ranges.  The results were fairly clean:

The low-voltage behavior of the nFET in the electret mic is not quite a linear resistor, and the saturation current definitely increases with voltage.

The low-voltage behavior of the nFET in the electret mic is not quite a linear resistor, and the saturation current definitely increases with voltage.

I tried extending the voltage range by using the power supply as well as the function generator: I set the function generator to a ±5V triangle wave, and used a -5V supply for the low-voltage reference. This worked well for the higher voltages, but the differential signal for the mic had an offset of about 12mV when the common-mode was -5V, which made the low-voltage measurements very wrong.  This offset may be correctable by recalibrating the scope (I am currently using the factory default settings, because I don’t have a voltmeter at home that I trust to be better than the factory settings), but I’m not counting on it.  When I need measurements of small signals, I’ll try to make sure that the common-mode is also small.

One other minor problem with the Analog Discovery 2: the female headers on the wires seem to have looser than usual springs, so that the wires easily fall off male header pins.  Given the stiffness of the wires, this is a bit

2016 December 12

FET I-vs-V with Analog Discovery 2

Filed under: Data acquisition — gasstationwithoutpumps @ 17:41
Tags: , , , ,

Yesterday, in FET Miller plateau with Analog Discovery 2, I started posting about the Analog Discovery 2 USB oscilloscope, an oscilloscope with two differential input channels, 2 arbitrary-waveform function generators, a dual regulated power supply, and a logic analyzer.

I want to modify something I said yesterday:

If I look at the square wave with nothing but the scope attached, then I see a voltage of about 4.005V.  With a 100Ω load, I see 3.44V, which gives an output impedance of 16.4Ω.

I think that what I was seeing should not really be characterized as an output impedance, but as a current limitation.  The AD8067 op-amp that is the output device for the waveform generator is specified to have a 30mA current limitation (for -60dB spurious-free dynamic range) and 105mA short-circuit current, and 3.44V/100Ω is 34.4mA.  I can test this assumption by seeing what happens with a triangle-wave signal:

The triangle wave with a 100Ω load is clipped at approximately ±3.48V, corresponding to a current limitation of ±34.8mA.

The triangle wave with a 100Ω load is clipped at approximately ±3.48V, corresponding to a current limitation of ±34.8mA.

With 100Ω, I get ±3.48V, for ±34.8mA.  With 33Ω, I get ±1.475V, for ±44.7mA.  With 18Ω, I get +1.014V, -0.8458V, for +56.3mA, -47mA.  In each case, I am getting clear clipping, not scaling of the signal, so the best model is as a 0Ω output impedance, combined with current limitation, rather than as a non-zero output impedance.  The current limitation is not quite constant—I can get more current at lower voltages.

Something else you can see in the image above is that the time axis is not limited to starting at 0—I can move the trigger point around either graphically or by typing into boxes that hold the trigger level and time position for the line in the middle of the screen.

What I really wanted to show today was not the waveform generator current limit, but Ids-vs-Vgs plots for an nFET (the same old AOI518 nFET that I was playing with yesterday). I can use the differential inputs to measure the gate-to-source voltage on one channel and voltage across a drain resistor on the second channel.  It is easy to adjust the voltage range for a slow triangle wave driving the gate, and to look at an XY plot:

Voltage across 20Ω drain resistor to 5V for AOI518 nFET for a range of gate-to-source voltages. To get the large current, an external 5V wall-wart had to be connected.

Voltage across 20Ω drain resistor to 5V for AOI518 nFET for a range of gate-to-source voltages. To get the large current, an external 5V wall-wart had to be connected.

It would be nice if there were a way to scale the voltages across the load resistor to plot currents on the XY plot, instead of just voltages.  I can, of course, do this scaling with external programs, as I have with other measurement devices. I tried changing the resistors to get different current ranges, exporting the data in tab-delimited formats, and plotting superimposed I-vs-V plots. The results were not as good as I’ve gotten in the past using PteroDAQ:

The Ids-vs-Vgs curves do not superimpose as nicely as curves I’ve measured with PteroDAQ. I don’t yet understand why not.

I’m also not sure why there seems to be a 4µA leakage current.  At the top end, I’m not hitting the current limit of the voltage regulator, which is 700mA when powered by an external power supply, as I did here.

2016 August 20

Using 4¢ diode for log-transimpedance

In Transimpedance pulse monitor does need low-pass, I realized that Schottky diodes were not going to work well for the transimpedance amplifier, and in Using nFET body diode for log-transimpedance, I tested using the body diode of a power nFET, finding that it worked quite well over at least 7.5 decades (from 1nA to 40mA).  But I wanted to see whether students could use a cheap 4¢ general-purpose diode.

I used the same setup as when testing the nFET body diodes.  The results were pretty much the same whether I used a 1N914B or 1N4148 diode (they share a datasheet, but the 1N914B has somewhat better constraints on the forward voltage):

The gain (in mV/dB) is about 85% larger than using an nFET body diode.

The gain (in mV/dB) is about 85% larger than using an nFET body diode.

Note that at currents over about 1mA the diode current starts to saturate, deviating from the exponential pattern.

Note that at currents over about 1mA the diode current starts to saturate, deviating from the exponential pattern.

When I tried using the 1N914B diode in the same log-transimpedance amplifier as I used for the nFET body diode, it didn’t work—I got output that looked nothing like a pulse (nor like 60Hz interference). I could recover proper behavior by putting a large (100nF) capacitor in parallel with the diode, to make a low-pass filter to remove signals above a few Hz, but that wasn’t necessary for the nFET body diode (perhaps it had enough internal capacitance to do the filtering). I could reduce the capacitor to 100pF, with 60Hz interference coming in, though not being too bad, but reducing to 10pF gave me noise again rather than the pulse signal.

I was hoping not to need that extra capacitor, because the design is already more complicated than I would like for this stage of the course, and figuring out what capacitor to use is difficult—trial and error is easier than rational design here!

I tried tracking down the big, short (less than 250µs) spikes that were corrupting the signal. The first thing I tried cleaned up the problem entirely: disconnecting the power supply from the laptop so that the USB power was coming from the laptop battery rather than the power supply . That this worked actually surprised me, since the 3.3V supply and the 1.65V Vref both had beefy bypass capacitors.

I don’t know whether the noise problems are in the microcontroller (which is providing the regulated 3.3V from the noisy USB 5V) or are coupled into the analog circuit some other way. Putting a 10µF capacitor from the USB5V to GND did not help when the power supply was connected, so perhaps the problem is radiated from the power-supply cable rather than conducted through the USB cable.

I’ve noticed problems before with noise from the laptop power supply causing problems in my analog circuits (the 90kHz interference in my ultrasound experiments), and I’ve see much bigger problems with some of the cheap Windows laptops students use. The bottom line, I guess, is that  I have to tell students to run PteroDAQ from battery power, not switching-supply power, even if the power supply seems more than adequately bypassed.

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