Inductive spikes

One of the labs in my textbook Applied Analog Electronics asks students to look at the inductive spikes created by switching a nFET on and off with a loudspeaker as a load:

A 5V pulse signal to Gn will turn the nFET on.

My students were very confused when they tried the experiment, because they got a different result:

What the students got at the nFET drain went a little above 5V, but did not have the enormous inductive spike they expected.

Of course, I lied to you a little about what their circuit was—they were working with half-H-bridge boards that they had soldered:

The half H-bridge boards have a pFET and capacitor on them, as well as an nFET.

The pFET was left unconnected, so the circuit was really the following:

The gate and pFET source were left floating in the student setups.

So what difference does the pFET make? Well, with the gate floating and staying near 0V, the pFET turns on when the pFET source voltage gets high enough, allowing the capacitor to charge.

The pFET source gets up to about 7.2–7.3V, and the time constants for the capacitor and loudspeaker are long enough that the capacitor looks like a power supply (not changing voltage much on this time scale), so that the body diode of the pFET snubs the inductive spike at about a diode drop above the pFET source voltage.

So how did I miss this problem when I did my testing before including the lab in the book? One possibility is that I left out the bypass capacitor—without it you get the expected spike. But I know I had included the capacitor on my half-H-bridge boards—I had to solder up a board without the bypass capacitor specially last night, in order to get the “expected” plot in the first plot of this post.  I think what happened is that when I had done my tests, I had always connected the pFET gate to the pFET source, to ensure that the pFET stayed off, but when I wrote the book, I forgot that in the instructions. Here are the plots of the board with the pFET gate and source tied together (both floating), both floating separately, and with the them both tied to 5V:

With the pFET gate and source tied together, the circuit behaves as expected, with large inductive spikes if the pFET source is floating, but snubbed to a diode drop above 5V if the source is tied to 5V.

The pFET source voltage gets quite high when the pFET gate and source are tied together to keep the FET off, but they are not tied to the power rail:

Because the pFET never turns on, the body diode and capacitor acts as a peak detector, and the capacitor charges until the leakage compensates for the charge deposited on each cycle, around 33.7V, snubbing the inductive spike at about 37V (more than a diode drop above, but the duration is short).

This summer and fall, when I’ll be working on the next edition of the book, I’ll be sure to improve the instructions for the FET lab!